74LS08 ,Quad 2-Input AND GatesDM74LS08 Quad 2-Input AND GatesAugust 1986Revised March 2000DM74LS08Quad 2-Input AND Gates
74LS09 ,Quad 2-Input AND Gates with Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains four independent gates each of w ..
74LS10 ,Triple 3-Input NAND GateGeneral DescriptionThis device contains three independent gates each ofwhich performs the logic NAN ..
74LS11 ,Triple 3-Input AND GateGeneral DescriptionThis device contains three independent gates each ofwhich performs the logic AND ..
74LS112 ,Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset/ Clear/ and Complementary OutputsSN54/74LS112ADUAL JK NEGATIVEEDGE-TRIGGERED FLIP-FLOPThe SN54/74LS112A dual JK flip-flop
74LS114A , DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
78A207-CP , MFR1 Receiver
78HT205HC , 2 AMP POSITIVE STEP-DOWN INTEGRATED SWITCHING REGULATOR
78L05 ,THREE TERMINAL POSITIVE VOLTAGE REGULATORSL78L00SERIES POSITIVE VOLTAGE REGULATORSn OUTPUT CURRENT UP TO 100 mAn OUTPUT VOLTAGESOF 3.3; 5; 6 ..
78L05A , 3-Terminal Regulators
78L05A , 3-Terminal Regulators
78L05A , 3-Terminal Regulators
74LS08-DM74LS08M-DM74LS08N
Quad 2-Input AND Gates
DM74LS08 Quad 2-Input AND Gates August 1986 Revised March 2000 DM74LS08 Quad 2-Input AND Gates General Description This device contains four independent gates each of which performs the logic AND function. Ordering Code: Order Number Package Number Package Description DM74LS08M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS08SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS08N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Y = AB Inputs Output AB Y LLL LH L HL L HH H H = HIGH Logic Level L = LOW Logic Level © 2000 DS006347
