DM74LS03N ,Quad 2-Input NAND Gates with Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains four independent gates each of w ..
DM74LS03N ,Quad 2-Input NAND Gates with Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains four independent gates each of w ..
DM74LS04J ,Hex Inverting Gates54LS04/DM54LS04/DM74LS04HexInvertingGatesJune198954LS04/DM54LS04/DM74LS04HexInvertingGatesGeneralDe ..
DM74LS04M ,Hex Inverting GatesFeaturesYAlternate Military/Aerospace device (54LS04) is avail-This device contains six independent ..
DM74LS04N ,Hex Inverting GatesGeneral DescriptionThis device contains six independent gates each of whichperforms the logic INVER ..
DM74LS04SJ ,Hex Inverting GatesGeneral DescriptionThis device contains six independent gates each of whichperforms the logic INVER ..
DS2119M ,Ultra3 LVD/SE SCSI TerminatorFUNCTIONAL DESCRIPTION The DS2119 combines LVD and SE termination with DIFFSENS sourcing and detect ..
DS2119M+ ,Ultra3 LVD/SE SCSI Terminator DS2119M Ultra3 LVD/SE SCSI Terminator PIN CONFIGURATION
DS2119ME ,Ultra3 LVD/SE SCSI TerminatorFUNCTIONAL DESCRIPTION The DS2119 combines LVD and SE termination with DIFFSENS sourcing and detect ..
DS2119ME ,Ultra3 LVD/SE SCSI TerminatorFUNCTIONAL DESCRIPTION The DS2119 combines LVD and SE termination with DIFFSENS sourcing and detect ..
DS2119ME ,Ultra3 LVD/SE SCSI TerminatorFEATURES Fully Compliant with SCSI SPI-2, SPI-3, SPI-4, Ultra160, and Ultra320 1 28 TPWRVREF R ..
DS2119ME ,Ultra3 LVD/SE SCSI Terminator DS2119M Ultra3 LVD/SE SCSI Terminator PIN CONFIGURATION
74LS03-DM74LS03M-DM74LS03N
Quad 2-Input NAND Gates with Open-Collector Outputs
DM74LS03 Quad 2-Input NAND Gates with Open-Collector Outputs August 1986 Revised March 2000 DM74LS03 Quad 2-Input NAND Gates with Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains four independent gates each of which performs the logic NAND function. The open-collector out- puts require external pull-up resistors for proper logical operation. Where: N (I ) = total maximum output high current 1 OH for all outputs tied to pull-up resistor N (I ) = total maximum input high current for 2 IH all inputs tied to pull-up resistor N (I ) = total maximum input low current for 3 IL all inputs tied to pull-up resistor Ordering Code: Order Number Package Number Package Description DM74LS03M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS03N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Y = AB Inputs Output AB Y LL H LH H HL H HH L H = HIGH Logic Level L = LOW Logic Level © 2000 DS006344
