74LCX74MTR ,CMOS DUAL D-TYPE FLIP FLOP WITH 5V TOLERANT INPUT74LCX74LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOPWITH 5V TOLERANT INPUTS ■ 5V TOLERANT INPUTS■ HIGH S ..
74LCX74MTR ,CMOS DUAL D-TYPE FLIP FLOP WITH 5V TOLERANT INPUTapplications; it can be interfaced to 5Vsignal environment for inputs.PIN CONNECTION AND IEC LOGIC ..
74LCX74MTR ,CMOS DUAL D-TYPE FLIP FLOP WITH 5V TOLERANT INPUTLOGIC DIAGRAM This
74LCX74MX ,Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant InputsFeaturesThe LCX74 is a dual D-type flip-flop with Asynchronous
74LCX74MTR-74LCX74TTR
CMOS DUAL D-TYPE FLIP FLOP WITH 5V TOLERANT INPUT
1/11September 2001 5V TOLERANT INPUTS HIGH SPEED : MAX = 150 MHz (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTIONThe 74LCX74 is a low voltage CMOS DUAL
D-TYPE FLIP FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for inputs.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of the
clock pulse.
CLR and PR are independent of the clock and
accomplished by a low setting on the appropriate
input.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LCX74LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP
WITH 5V TOLERANT INPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74LCX742/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
74LCX743/11
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
RECOMMENDED OPERATING CONDITIONS 1) Truth Table guaranteed: 1.5V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
74LCX744/11
DC SPECIFICATIONS
DYNAMIC SWITCHING CHARACTERISTICS 1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
74LCX745/11
AC ELECTRICAL CHARACTERISTICS 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per
Flip-Flop)
74LCX746/11
TEST CIRCUIT CL = 50 pF or equivalent (includes jig and probe capacitance)
RL = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
