74LCX652 ,CMOS OCTAL BUS TRANSCEIVER/REGISTER WITH 5V TOLERANT INPUT AND OUTPUTapplications; it can be interfaced to 5V signal When select AB and select BA are in the real-timeen ..
74LCX652M ,CMOS OCTAL BUS TRANSCEIVER/REGISTER WITH 5V TOLERANT INPUT AND OUTPUT74LCX652LOW VOLT. CMOS OCTAL BUS TRANSCEIVER/REGISTERWITH 5 VOLT TOLERANT INPUTS AND OUTPUTS(3-STAT ..
74LCX652M ,CMOS OCTAL BUS TRANSCEIVER/REGISTER WITH 5V TOLERANT INPUT AND OUTPUTapplications; it can be interfaced to 5V signal When select AB and select BA are in the real-timeen ..
74LCX652MSAX ,Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputsapplications with capability of interfacing to a 5V signal
74LCX652
CMOS OCTAL BUS TRANSCEIVER/REGISTER WITH 5V TOLERANT INPUT AND OUTPUT
1/16September 2004 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED:
tPD = 7.0 ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 652 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTIONThe 74LCX652 is a low voltage CMOS OCTAL
BUS TRANSCEIVER AND REGISTER
(3-STATE) fabricated with sub-micron silicon gate
and double-layer metal wiring C2 MOS technology.
It is ideal for low power and high speed 3.3V
applications; it can be interfaced to 5V signal
environment for both inputs and outputs.
This device consists of bus transceiver circuits
with 3 state, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data
directly from the input bus or from the internal
storage registers. Enable (GAB) and (GBA) pins
are provided to control the transceiver functions.
Select AB and Select BA control pins are provided
to select whether real-time or stored data is
transferred. A low input level selects real-time,
and a high selects stored data.
Data on the A or B bus, or both, can be stored in
the internal D flip-flop by low to high transitions at
the appropriate clock pins (CAB or CBA)
regardless of the select or enable control pins.
When select AB and select BA are in the real-time
transfer mode, it is also possible to store data
74LCX652LOW VOLT. CMOS OCTAL BUS TRANSCEIVER/REGISTER
WITH 5 VOLT TOLERANT INPUTS AND OUTPUTS(3-STATE)
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes Rev. 6
M74LCX6522/16
without using the internal D-type flip-flops by
simultaneously enabling GAB or GBA. In this
configuration each output reinforces its input.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
M74LCX6523/16
Table 3: Truth Table X : Don’t Care
Z : High Impedance
Qn : The data stored to the internal flip-flops by most recent low to high transition of the clock inputs
* : The data at the A and B bus will be stored to the internal flip-flops on every low to high transition of the clock inputs.
M74LCX652
Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays
Figure 4: Timing Chart
M74LCX6525/16
Table 4: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
Table 5: Recommended Operating Conditions 1) Truth Table guaranteed: 1.5V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
M74LCX6526/16
Table 6: DC Specifications
Table 7: Dynamic Switching Characteristics 1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
M74LCX6527/16
Table 8: AC Electrical Characteristics 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
Table 9: Capacitive Characteristics 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit)
M74LCX6528/16
Figure 5: Test Circuit CL = 50 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 6: Waveform - Propagation Delay Times (f=1MHz; 50% duty cycle)
