74LCX646M ,CMOS OCTAL BUS TRANSCEIVER/REGISTER WITH 5V TOLERANT INPUT AND OUTPUT74LCX646LOW VOLT. CMOS OCTAL BUS TRANSCEIVER/REGISTERWITH 5 VOLT TOLERANT INPUTS AND OUTPUTS(3-STAT ..
74LCX646MSAX ,Low Voltage Octal Transceiver/Register with 5V Tolerant Inputs and Outputsapplications with capability of interfacing to a 5V signal
74LCX646M
CMOS OCTAL BUS TRANSCEIVER/REGISTER WITH 5V TOLERANT INPUT AND OUTPUT
1/13September 2001 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED :
tPD = 7.0 ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:CC (OPR) = 2.0V to 3.6V (1.5V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 646 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTIONThe 74LCX646 is a low voltage CMOS OCTAL
BUS TRANSCEIVER AND REGISTER
(3-STATE) fabricated with sub-micron silicon gate
and double-layer metal wiring C2 MOS technology.
It is ideal for low power and high speed 3.3V
applications; it can be interfaced to 5V signal
environment for both inputs and outputs.
This device consists of bus transceiver circuits
with 3 state, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data
directly from the input bus or from the internal
registers. Data on the A or B bus will be clocked
into register on the low to high transition of the
appropriate clock pin (Clock AB or Clock BA).
Enable (G) and direction (DIR) pins are provided
to control the transceiver functions. In the
transceiver mode, data present at the
high-impedance port may be stored in either
register or in both. The select controls (Select AB
select BA) can multiplex stored and real time
(transparent mode) data. The direction control
determines which bus will receive data when
enable G is active (low). In the isolation mode
74LCX646LOW VOLT. CMOS OCTAL BUS TRANSCEIVER/REGISTER
WITH 5 VOLT TOLERANT INPUTS AND OUTPUTS(3-STATE)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74LCX6462/13
(enable G high), "A" data may be stored in one
register and/or "B" data may be stored in the other
register. When an output function is disabled, the
input function is still enabled and may be used to
store and transmit data. Only one of the two
buses, A or B, may be driven at a time. It has
same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
M74LCX6463/13
TRUTH TABLE X : Don’t Care
Z : High Impedance
Qn : The data stored to the internal flip-flops by most recent low to high transition of the clock inputs
* : The data at the A and B bus will be stored to the internal flip-flops on every low to high transition of the clock inputs.
M74LCX6464/13
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
TIMING CHART
M74LCX6465/13
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
RECOMMENDED OPERATING CONDITIONS 1) Truth Table guaranteed: 1.5V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
M74LCX6466/13
DC SPECIFICATIONS
DYNAMIC SWITCHING CHARACTERISTICS 1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
M74LCX6467/13
AC ELECTRICAL CHARACTERISTICS 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit)
