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74LCX245MSTN/a1040avaiLOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
74LCX245MTRSTN/a1277avaiLOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
74LCX245TTRSTN/a345avaiLOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS


74LCX245MTR ,LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTSapplications; it can beAll floating bus terminals during High Z state mustinterfaced to 5V signal e ..
74LCX245SJ ,Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and OutputsElectrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-me ..
74LCX245SJX ,Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputsapplications with capability of interfacing toCC

74LCX245M-74LCX245MTR-74LCX245TTR
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
1/10September 2001 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED :PD = 7.0 ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 245 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION

The 74LCX245 is a low voltage CMOS OCTAL
BUS TRANSCEIVER (3-STATE) fabricated with
sub-micron silicon gate and double-layer metal
wiring C2 MOS technology. It is ideal for low power
and high speed 3.3V applications; it can be
interfaced to 5V signal environment for both inputs
and outputs.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
This IC is intended for two way asynchronous
communication between data buses; the direction
of data transmission is determined by DIR input.
The enable input G can be used to disable the
device so that the buses are effectively isolated.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
All floating bus terminals during High Z state must
be held HIGH or LOW.
74LCX245

LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER(3-STATE)
WITH 5V TOLERAT INPUTS AND OUTPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74LCX245
2/10
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE

X : Don’t Care
Z : High Impedance
74LCX245
3/10
ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
RECOMMENDED OPERATING CONDITIONS

1) Truth Table guaranteed: 1.5V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
74LCX245
4/10
DC SPECIFICATIONS
DYNAMIC SWITCHING CHARACTERISTICS

1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
74LCX245
5/10
AC ELECTRICAL CHARACTERISTICS

1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit)
74LCX245
6/10
TEST CIRCUIT

CL = 50 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
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