74LCX241 ,Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputsapplications with capa-CC
74LCX241
Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
74LCX241 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs August 1998 Revised July 2002 74LCX241 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs General Description Features The LCX241 is an octal buffer and line driver designed to5V tolerant inputs and outputs be employed as a memory address driver, clock driver and2.3V – 3.6V V specifications provided CC bus oriented transmitter or receiver. The device is designed 6.5 ns t max (V = 3.3V), 10 μA I max PD CC CC for low voltage (2.5V or 3.3V) V applications with capa- CC Power-down high impedance inputs and outputs bility of interfacing to a 5V signal environment. Supports live insertion/withdrawal (Note 1) The LCX241 is fabricated with an advanced CMOS tech- nology to achieve high speed operation while maintainingImplements patented noise/EMI reduction circuitry CMOS low power dissipation. Latch-up performance exceeds 500 mA ESD performance: Human Body Model > 2000V Machine Model > 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to V and OE should be tied to GND through a resistor: the CC minimum value or the resistor is determined by the current-sourcing capa- bility of the driver. Ordering Code: Order Number Package Number Package Description 74LCX241WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LCX241SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX241MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LCX241MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description OE , OE 3-STATE Output Enable Inputs 1 2 I –I Inputs 0 7 O –O Outputs 0 7 © 2002 DS012639
