74LCX16841MTDX ,Low Voltage 20-Bit Transparent Latch with 5V Tolerant Inputs and OutputsFunctional DescriptionThe LCX16841 contains twenty D-type latches with its D input changes. When LE ..
74LCX16841MTDX ,Low Voltage 20-Bit Transparent Latch with 5V Tolerant Inputs and OutputsFeaturesThe LCX16841 contains twenty non-inverting latches with
74LCX16841MTD-74LCX16841MTDX
Low Voltage 20-Bit Transparent Latch with 5V Tolerant Inputs and Outputs
74LCX16841 Low Voltage 20-Bit Transparent Latch with 5V Tolerant Inputs and Outputs October 1995 Revised April 2001 74LCX16841 Low Voltage 20-Bit Transparent Latch with 5V Tolerant Inputs and Outputs General Description Features The LCX16841 contains twenty non-inverting latches with5V tolerant inputs and outputs 3-STATE outputs and is intended for bus oriented applica-2.3V–3.6V V specifications provided CC tions. The device is byte controlled. The flip-flops appear 5.5 ns t max (V = 3.3V), 20 μA I max PD CC CC transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup timePower down high impedance inputs and outputs is latched. Data appears on the bus when the OutputSupports live insertion/withdrawal (Note 1) Enable (OE) is LOW. When OE is HIGH, the outputs are in ±24 mA output drive (V = 3.0V) CC a high impedance state. Implements patented noise/EMI reduction circuitry The LCX16841 is designed for low voltage (2.5V or 3.3V) Latch-up performance exceeds 500 mA V applications with capability of interfacing to a 5V signal CC environment.ESD performance: Human body model > 2000V The LCX16841 is fabricated with an advanced CMOS tech- nology to achieve high speed operation while maintaining Machine model > 200V CMOS low power dissipation. Note 1: To ensure the high-impedance state during power up or down, OE should be tied to V through a pull-up resistor: the minimum value or the CC resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74LCX16841MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 74LCX16841MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) n LE Latch Enable Input n D –D Inputs 0 19 O –O Outputs 0 19 © 2001 DS012578
