74LCX16374 ,LOW VOLTAGE 16-BIT D-TYPE FLIP FLOP 3-STATE WITH 5V TOLLERANT INPUTS AND OUTPUTSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LCX16374G ,Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputsapplications. The device is byte controlled. A buff-
74LCX16374
LOW VOLTAGE 16-BIT D-TYPE FLIP FLOP 3-STATE WITH 5V TOLLERANT INPUTS AND OUTPUTS
1/10February 2003 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED:
fMAX= 150MHz (MIN.)at VCC =3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|= IOL= 24mA (MIN)at VCC =3V PCI BUS LEVELS GUARANTEED AT24 mA BALANCED PROPAGATION DELAYS:
tPLH≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR)= 2.0Vto 3.6V (1.5V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH SERIES 16374 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM> 2000V (MIL STD 883 method 3015);> 200V
DESCRIPTIONThe 74LCX16374isa low voltage CMOS 16 BIT
D-TYPE FLIP-FLOP with3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiringC2 MOS
technology.Itis ideal for low power and high
speed 3.3V applications;it canbe interfacedto 5V
signal environment for both inputs and outputs.
These 16 bit D-TYPE flip-flops are controlled by
two clock inputs (nCK) and two output enablein-
puts(nOE). On the positive transitionof the (nCK),
the nQ outputs will be setto the logic state that
were setupat the nD inputs. While the (nOE) input low, the8 outputs (nQ) willbeina normal state
(highor low logic level) and while high level the
outputs willbeina high impedance state.
Any output control does not affect the internal op-
erationof flip flops; thatis, the old data canbe re-
tainedor the new data canbe entered even while
the outputs are off. has same speed performanceat 3.3V than 5V
AC/ACT family, combined witha lower power
consumption.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
74LCX16374LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
ORDER CODES
PIN CONNECTION
74LCX163742/10
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE: Don‘t Care: High Impedance
IEC LOGIC SYMBOLS
74LCX163743/10
LOGIC DIAGRAMThis logic diagramhasnottobe usedto estimate propagation delays
ABSOLUTE MAXIMUM RATINGSAbsoluteMaximum Ratingsare those values beyond which damagetothe device mayoccur.Functional operation under these conditionsis
not impliedIO absolute maximum rating mustbe observedVO
RECOMMENDED OPERATING CONDITIONS Truth Table guaranteed: 1.5Vto 3.6VVIN from 0.8Vto2Vat VCC =3.0V
74LCX16374
4/10 SPECIFICATIONS
DYNAMIC SWITCHING CHARACTERISTICS Numberof outputs definedas"n". Measured with "n-1" outputs switching from HIGHto LOWor LOWto HIGH. The remaining outputis
measuredinthe LOW state.
74LCX16374
5/10 ELECTRICAL CHARACTERISTICS Skewis defined astheabsolute value ofthedifference betweenthe actual propagation delayfor anytwo outputsofthe samedevice switch-
inginthe same direction, either HIGHor LOW (tOSLH =|tPLHm -tPLHn|, tOSHL =|tPHLm -tPHLn|) Parameter guaranteedby design
CAPACITIVE CHARACTERISTICS CPD isdefinedasthe valueofthe IC’s internal equivalent capacitance whichis calculatedfrom theoperating current consumption without
load. (Referto Test Circuit). Average operating currentcanbe obtainedbythe following equation. ICC(opr) =CPD xVCC xfIN +ICC/16 (per
circuit)
74LCX16374
6/10
TEST CIRCUIT=50pFor equivalent (includesjig and probe capacitance) =R1= 500Ω or equivalent =ZOUTof pulse generator (typically 50Ω)
WAVEFORM1: PROPAGATION DELAYS, SETUP AND HOLD TIMES, MAXIMUM CLOCK
FREQUENCY (f=1MHz; 50% duty cycle)
