74LCX138 ,LOW VOLTAGE CMOS 3 TO 8 LINE DECODER (INV.) WITH 5V TOLERANT INPUTSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LCX138BQX ,Low Voltage 1-of-8 Decoder/Demultiplexer with 5V Tolerant InputsFeaturesThe LCX138 is a high-speed 1-of-8 decoder/demultiplexer.
74LCX138
LOW VOLTAGE CMOS 3 TO 8 LINE DECODER (INV.) WITH 5V TOLERANT INPUTS
1/12September 2004 5V TOLERANT INPUTS HIGH SPEED:
tPD = 6.7ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTIONThe 74LCX138 is a low voltage CMOS 3 TO 8
LINE DECODER (INVERTING) fabricated with
sub-micron silicon gate and double-layer metal
wiring C2 MOS technology. It is ideal for low power
and high speed 3.3V applications; it can be
interfaced to 5V signal environment for inputs.
If the device is enabled, 3 binary select inputs (A,
B and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
Three enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LCX138LOW VOLTAGE CMOS 3 TO 8 LINE DECODER (INV.)
WITH 5V TOLERANT INPUTS
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes Rev. 4
74LCX1382/12
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
Table 3: Truth Table X : Don’t Care
74LCX1383/12
Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays
Table 4: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
74LCX1384/12
Table 5: Recommended Operating Conditions 1) Truth Table guaranteed: 1.5V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
Table 6: DC Specifications
Table 7: Dynamic Switching Characteristics 1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
74LCX1385/12
Table 8: AC Electrical Characteristics 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
Table 9: Capacitive Characteristics 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
Figure 4: Test Circuit CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74LCX1386/12
Figure 5: Waveform - Propagation Delays For Inverting Outputs (f=1MHz; 50% duty cycle)
Figure 6: Waveform - Propagation Delays For Non-inverting Outputs (f=1MHz; 50% duty cycle)
