74LCX125 ,CMOS QUAD BUS BUFFERS WITH 5V TOLERANT INPUT AND OUTPUTapplications; it can be interfaced to 5V
74LCX125
CMOS QUAD BUS BUFFERS WITH 5V TOLERANT INPUT AND OUTPUT
1/12September 2004 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED:
tPD = 5.2 ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:CC (OPR) = 2.0V to 3.6V (1.5V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTIONThe 74LCX125 is a low voltage CMOS QUAD
BUS BUFFER fabricated with sub-micron silicon
gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
The device requires the 3-STATE control input G
to be set high to place the output in to the high
impedance state.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LCX125LOW VOLTAGE CMOS QUAD BUS BUFFER (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes Rev. 5
74LCX1252/12
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description Table 3: Truth Table X : Don’t Care
Z : High Impedance
Table 4: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
74LCX1253/12
Table 5: Recommended Operating Conditions 1) Truth Table guaranteed: 1.5V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
Table 6: DC Specifications
74LCX1254/12
Table 7: Dynamic Switching Characteristics 1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
Table 8: AC Electrical Characteristics 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
Table 9: Capacitive Characteristics 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per gate)
74LCX1255/12
Figure 3: Test Circuit CL = 50 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 4: Waveform - Propagation Delay (f=1MHz; 50% duty cycle)
74LCX1256/12
Figure 5: Waveform - Output Enable And Disable Time (f=1MHz; 50% duty cycle)
