74LCX112 ,Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant InputsFeaturesThe LCX112 is a dual J-K flip-flop. Each flip-flop has inde-
74LCX112
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs June 1998 Revised February 2001 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has inde-5V tolerant inputs pendent J, K, PRESET, CLEAR, and CLOCK inputs with Q,2.3V–3.6V V specifications provided CC Q outputs. These devices are edge sensitive and change 7.5 ns t max (V = 3.3V), 10 μA I max PD CC CC state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accom-Power down high impedance inputs and outputs plished by a low logic level on the corresponding input.±24 mA output drive (V = 3.0V) CC LCX devices are designed for low voltage (3.3V or 2.5) Implements patented noise/EMI reduction circuitry operation with the added capability of interfacing to a 5V Latch-up performance exceeds 500 mA signal environment. ESD performance: The 74LCX112 is fabricated with advanced CMOS technol- ogy to achieve high speed operation while maintaining Human body model > 2000V CMOS low power dissipation. Machine model > 2000V Ordering Code: Order Number Package Number Package Description 74LCX112M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74LCX112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX112MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description J , J , K , K Data Inputs 1 2 1 2 CP , CP Clock Pulse Inputs (Active Falling Edge) 1 2 C , C Direct Clear Inputs (Active LOW) D1 D2 S , S Direct Set Inputs (Active LOW) D1 D2 Q , Q , Q , Q Outputs 1 2 1 2 © 2001 DS012424
