74LCX10MX ,Low Voltage Triple 3-Input NAND Gate with 5V Tolerant InputsFeaturesThe LCX10 contains three 3-input NAND gates. The inputs
74LCX10MTC-74LCX10MTCX-74LCX10MX
Low Voltage Triple 3-Input NAND Gate with 5V Tolerant Inputs
74LCX10 Low Voltage Triple 3-Input NAND Gate with 5V Tolerant Inputs June 2000 Revised February 2005 74LCX10 Low Voltage Triple 3-Input NAND Gate with 5V Tolerant Inputs General Description Features The LCX10 contains three 3-input NAND gates. The inputs5V tolerant inputs tolerate voltages up to 7V allowing the interface of 5V sys-2.3V–3.6V V specifications provided CC tems to 3V systems. 4.9 ns t max (V 3.3V), 10 PA I max PD CC CC The 74LCX10 is fabricated with advanced CMOS technol- Power down high impedance inputs and outputs ogy to achieve high speed operation while maintaining CMOS low power dissipation.r24 mA output drive (V 3.0V) CC Implements patented noise/EMI reduction circuitry Latch-up performance exceeds 500 mA ESD performance: Human body model ! 2000V Machine model ! 200V Ordering Code: Order Number Package Number Package Description 74LCX10M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LCX10SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX10MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Truth Table O A B C Pin Names Description n n n n A , B , C Inputs n n n A B C O n n n n O Outputs n XX L H XL X H LX X H HHH L H HIGH Voltage Level X Immaterial L LOW Voltage Level © 2005 DS500453
