74LCX02MX ,Low Voltage Quad 2-Input NOR Gate with 5V Tolerant Inputs74LCX02 Low Voltage Quad 2-Input NOR Gate with 5V Tolerant InputsMarch 1995Revised January 200574LC ..
74LCX02SJ ,Low Voltage Quad 2-Input NOR Gate with 5V Tolerant InputsElectrical CharacteristicsV T = −40°C to +85°CCC ASymbol Parameter Conditions Units(V) Min MaxV HIG ..
74LCX02SJX ,Low Voltage Quad 2-Input NOR Gate with 5V Tolerant InputsElectrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommen ..
74LCX02SJX ,Low Voltage Quad 2-Input NOR Gate with 5V Tolerant InputsFeaturesThe LCX02 contains four 2-input NOR gates. The inputs
74LCX02M-74LCX02MTC-74LCX02MTCX-74LCX02MX-74LCX02SJ-74LCX02SJX
Low Voltage Quad 2-Input NOR Gate with 5V Tolerant Inputs
74LCX02 Low Voltage Quad 2-Input NOR Gate with 5V Tolerant Inputs March 1995 Revised January 2005 74LCX02 Low Voltage Quad 2-Input NOR Gate with 5V Tolerant Inputs General Description Features The LCX02 contains four 2-input NOR gates. The inputs5V tolerant inputs tolerate voltages up to 7V allowing the interface of 5V sys-2.3V–3.6V V specification provided CC tems to 3V systems. 5.2 ns t max (V = 3.3V), 10 μA I max PD CC CC The 74LCX02 is fabricated with advanced CMOS technol- Power down high impedance inputs and outputs ogy to achieve high speed operation while maintaining CMOS low power dissipation.±24 mA output drive (V = 3.0V) CC Implements patented noise/EMI reduction circuitry Latch-up performance exceeds 500 mA ESD performance: Human body model > 2000V Machine model > 200V Ordering Code: Package Order Number Package Description Number 74LCX02M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LCX02SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX02MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LCX02MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, (Note 1) 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” package available in Tape and Reel only. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description A , B Inputs n n O Outputs n © 2005 ds012409
