74HCT534D Fast Delivery |IC PHOENIX CO.,LIMITED

74HCT534D ,74HCT534; 5 V octal D-type flip-flop; positive-edge trigger; 3-state; invertingapplications■ 8-bit positive-edge triggered register■ Common 3-state output enable input.3. Quick r ..
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74HCT534D
74HCT534; 5 V octal D-type flip-flop; positive-edge trigger; 3-state; inverting
General descriptionThe 74HCT534 is a high-speed Si-gate CMOS device and is pin compatible with low
power Schottky TTL (LSTTL). The 74HCT534 is speciﬁed in compliance with JEDEC
standard no. 7A.
The 74HCT534 is an octal D-type ﬂip-ﬂop featuring separate D-type inputs for each
ﬂip-ﬂop and inverting 3-state outputs for bus oriented applications. A clock (CP) and an
output enable (OE) input are common to all ﬂip-ﬂops.
The8 ﬂip-ﬂops will store the stateof their individual D-inputs that meet the set-up and hold
times requirementson the LOW-to-HIGH CP transition. When OEis LOW, the contentsof
the 8 ﬂip-ﬂops are available at the outputs. When OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input does not affect the state of the
ﬂip-ﬂops.
The 74HCT534 is functionally identical to the 74HCT374, but has inverted outputs. Features 3-state inverting outputs for bus oriented applications 8-bit positive-edge triggered register Common 3-state output enable input. Quick reference data
[1] CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
74HCT534 V octal D-type ﬂip-ﬂop; positive-edge trigger; inverting;
3-state
Table 1: Quick reference data
GND=0 V; Tamb =25 °C; tr =tf=6 ns.
tPHL, tPLH propagation delayto Qn=15 pF; VCC=5V - 13 - ns
fmax maximum clock
frequency=15 pF; VCC=5V - 40 - MHz input capacitance - 3.5 - pF
CPD power dissipation
capacitance per ﬂip-ﬂop=50 pF; VCC= 4.5V [1][2] -19 - pF
Philips Semiconductors 74HCT534
VCC= supply voltage in Volts;= number of inputs switching;
Σ(CL× VCC2×fo)= sum of the outputs.
[2] The condition is VI= GND to VCC−1.5V. Ordering information Functional diagram
Table 2: Ordering information
74HCT534N −40°Ct0 +125°C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HCT534D −40°Ct0 +125°C SO20 plastic small outline package; 20 leads; body
width 7.5 mm
SOT163-1
Philips Semiconductors 74HCT534
Philips Semiconductors 74HCT534 Pinning information
6.1 Pinning
6.2 Pin description
Table 3: Pin description 1 3-state output enable input (active LOW) 2 3-state output 3 data input 4 data input 5 3-state output 6 3-state output 7 data input 8 data input 9 3-state output
GND 10 ground (0V) 11 clock input (LOW-to-HIGH, edge-triggered) 12 3-state output 13 data input 14 data input 15 3-state output 16 3-state output 17 data input 18 data input 19 3-state output
VCC 20 supply voltage
Philips Semiconductors 74HCT534 Functional description
7.1 Function table
[1]H= HIGH voltage level;= HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;= LOW voltage level;= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;= high-impedance OFF-state;= LOW-to-HIGH clock transition. Limiting values
[1] Above 70 °C: Ptot derates linearly with 12 mW/K.
[2] Above 70 °C: Ptot derates linearly with 8 mW/K. Recommended operating conditions
Table 4: Function table[1]
Load and read
register ↑ lL H ↑ hH L
Load register and
disable outputs ↑ lL Z ↑ hH Z
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
VCC supply voltage −0.5 +7 V
IIK input diode current VI < −0.5 V or VI >VCC+ 0.5 V - ±20 mA
IOK output diode current VO< −0.5 V or >VCC+ 0.5V ±20 mA output source or sink
current
VO = −0.5 V to VCC+ 0.5V - ±35 mA
ICC, IGND VCC or GND current - ±70 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation
DIP20 package [1]- 750 mW
SO20 package [2]- 500 mW
Table 6: Recommended operating conditions
VCC supply voltage 4.5 5.0 5.5 V input voltage 0 - VCC V
Philips Semiconductors 74HCT534
10. Static characteristics output voltage 0 - VCC V
tr, tf input rise and fall
times
VCC = 4.5 V - 6.0 500 ns
Tamb ambient
temperature
see Section 10 and11 −40 - +125 °C
Table 6: Recommended operating conditions …continued
Table 7: Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb =25°C
VIH HIGH-level input voltage VCC= 4.5 V to 5.5V 2.0 1.6 - V
VIL LOW-level input voltage VCC= 4.5 V to 5.5V - 1.2 0.8 V
VOH HIGH-level output voltage VI =VIHor VIL; VCC= 4.5V= −20μA 4.4 4.5 - V=−6 mA 3.98 4.32 - V
VOL LOW-level output voltage VI =VIHor VIL; VCC= 4.5V =20μA - 0 0.1 V= 6.0 mA - 0.16 0.26 V
ILI input leakage current VI =VCCor GND; VCC= 5.5V - - ±0.1 μA
IOZ 3-state OFF current VI =VIHor VIL; other inputs
VCCor GND; VO =VCCor GND; =0A ±0.5 μA
ICC quiescent supply current VI =VCCor GND; IO =0A;
VCC= 5.5V - 8.0 μA
ΔICC additional quiescent supply
current per input pin =VCC− 2.1 V; other inputs =VCCor GND;
VCC= 4.5Vto 5.5 V; IO =0A
pin OE - 125 450 μA
pin CP - 90 325 μA
pins Dn - 35 125 μA input capacitance - 3.5 - pF
Tamb= −40 °C to +85°C
VIH HIGH-level input voltage VCC= 4.5 V to 5.5V 2.0 - - V
VIL LOW-level input voltage VCC= 4.5 V to 5.5V - - 0.8 V
VOH HIGH-level output voltage VI =VIHor VIL; VCC= 4.5V= −20μA 4.4 - - V=−6 mA 3.84 - - V
VOL LOW-level output voltage VI =VIHor VIL; VCC= 4.5V =20μA - - 0.1 V= 6.0 mA - - 0.33 V
ILI input leakage current VI =VCCor GND; VCC= 5.5V - - ±1.0 μA
Philips Semiconductors 74HCT534
11. Dynamic characteristics
IOZ 3-state OFF current VI =VIHor VIL; other inputs
VCCor GND; VO =VCCor GND; =0A ±5 μA
ICC quiescent supply current VI =VCCor GND; IO =0A;
VCC= 5.5V
--80 μA
ΔICC additional quiescent supply
current per input pin =VCC− 2.1 V; other inputs =VCCor GND;
VCC= 4.5Vto 5.5 V; IO =0A
pin OE - - 560 μA
pin CP - - 405 μA
pins Dn - - 155 μA
Tamb= −40 °C to +125°C
VIH HIGH-level input voltage VCC= 4.5 V to 5.5V 2.0 - - V
VIL LOW-level input voltage VCC= 4.5 V to 5.5V - - 0.8 V
VOH HIGH-level output voltage VI =VIHor VIL; VCC= 4.5V= −20μA 4.4 - - V=−6 mA 3.7 - - V
VOL LOW-level output voltage VI =VIHor VIL; VCC= 4.5V =20μA - - 0.1 V= 6.0 mA - - 0.4 V
ILI input leakage current VI =VCCor GND; VCC= 5.5V - - ±1.0 μA
IOZ 3-state OFF current VI =VIHor VIL; other inputs
VCCor GND; VO =VCCor GND; =0A ±10 μA
ICC quiescent supply current VI =VCCor GND; IO =0A;
VCC= 5.5V - 160 μA
ΔICC additional quiescent supply
current per input pin =VCC− 2.1 V; other inputs =VCCor GND;
VCC= 4.5Vto 5.5 V; IO =0A
pin OE - - 610 μA
pin CP - - 440 μA
pins Dn - - 170 μA
Table 7: Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Table 8: Dynamic characteristics
GND=0 V; VCC= 4.5 V; tr =tf=6 ns; CL=50 pF; see Figure9
Tamb =25°C
tPHL, tPLH propagation delay CP toQn see Figure6=50 pF; VCC= 4.5V - 16 30 ns=15 pF; VCC=5V - 13 -
tPZH, tPZL 3-state output enable time OEto Qn see Figure7 - 1630ns
Philips Semiconductors 74HCT534
[1] CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in Volts;= number of inputs switching;
Σ(CL× VCC2×fo)= sum of the outputs.
[2] The condition is VI= GND to VCC−1.5V.
tPHZ, tPLZ 3-state output disable time OEto Qn see Figure7 - 1830ns
tTHL, tTLH output transition time see Figure6 - 5 12 ns clock pulse width HIGH or LOW see Figure6 23 14 - ns
tsu set-up time Dn to CP see Figure8 12 4 - ns hold time Dn to CP see Figure8 5 −1- ns
fmax maximum clock pulse frequency see Figure6=50 pF; VCC= 4.5V 22 36 - MHz=15 pF; VCC=5V - 40 - MHz
CPD power dissipation capacitance per
ﬂip-ﬂop
[1][2] -19 - pF
Tamb= −40°Cto +85°C
tPHL, tPLH propagation delay CP toQn see Figure6 --38 ns
tPZH, tPZL 3-state output enable time OEto Qn see Figure7 --38 ns
tPHZ, tPLZ 3-state output disable time OEto Qn see Figure7 --38 ns
tTHL, tTLH output transition time see Figure6 --15 ns clock pulse width HIGH or LOW see Figure6 29 --ns
tsu set-up time Dn to CP see Figure8 15 --ns hold time Dn to CP see Figure8 5 --ns
fmax maximum clock pulse frequency see Figure6 18 - - MHz
Tamb= −40°Cto +125°C
tPHL, tPLH propagation delay CP toQn see Figure6 --45 ns
tPZH, tPZL 3-state output enable time OEto Qn see Figure7 --45 ns
tPHZ, tPLZ 3-state output disable time OEto Qn see Figure7 --45 ns
tTHL, tTLH output transition time see Figure6 --18 ns clock pulse width HIGH or LOW see Figure6 35 --ns
tsu set-up time Dn to CP see Figure8 18 --ns hold time Dn to CP see Figure8 5 --ns
fmax maximum clock pulse frequency see Figure6 15 - - MHz
Table 8: Dynamic characteristics …continued
GND=0 V; VCC= 4.5 V; tr =tf=6 ns; CL=50 pF; see Figure9

Partno	Mfg	Dc	Qty	Available	Descript
74HCT534D	PHILIPS	N/a	6	avai	74HCT534; 5 V octal D-type flip-flop; positive-edge trigger; 3-state; inverting