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74HC86DB-74HC86PW-74HCT86PW
Quad 2-input EXCLUSIVE-OR gate
Philips Semiconductors Product specification
Quad 2-input EXCLUSIVE-OR gate 74HC/HCT86
FEATURES Output capability: standard ICC category: SSI
GENERAL DESCRIPTIONThe 74HC/HCT86 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT86 provide the EXCLUSIVE−OR function.
QUICK REFERENCE DATAGND= 0 V; Tamb =25 °C; tr =tf= 6 ns
Notes CPD is used to determine the dynamic power dissipation (PD in μW): =CPD× VCC2×fi +∑ (CL× VCC2× fo) where:= input frequency in MHz= output frequency in MHz (CL× VCC2×fo)= sum of outputs= output load capacitance in pF
VCC= supply voltage in V For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATIONSee “74HC/HCT/HCU/HCMOS Logic Package Information”.
Philips Semiconductors Product specification
Quad 2-input EXCLUSIVE-OR gate 74HC/HCT86
PIN DESCRIPTION
Philips Semiconductors Product specification
Quad 2-input EXCLUSIVE-OR gate 74HC/HCT86
FUNCTION TABLE
Notes H= HIGH voltage level= LOW voltage level
Philips Semiconductors Product specification
Quad 2-input EXCLUSIVE-OR gate 74HC/HCT86
DC CHARACTERISTICS FOR 74HCFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HCGND= 0 V; tr =tf= 6 ns; CL= 50 pF
DC CHARACTERISTICS FOR 74HCTFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: SSI
Notes to HCT typesThe value of additional quiescent supply current (ΔICC) for a unit load of 1 is given in the family specifications.
To determine ΔICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCTGND= 0 V; tr =tf= 6 ns; CL= 50 pF
Philips Semiconductors Product specification
Quad 2-input EXCLUSIVE-OR gate 74HC/HCT86
AC WAVEFORMS
PACKAGE OUTLINESSee “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
