74HC74N-74HC74PW-74HCT74PW Fast Delivery |IC PHOENIX CO.,LIMITED

74HCT74PW ,Dual D-type flip-flop with set and reset; positive-edge triggerLogic diagram for one flip-flop74HC_HCT74 All information provided in this document is subject to l ..
74HCT75 ,Quad bistable transparent latch
74HCT7540D ,Octal Schmitt trigger buffer/line driver; 3-state; invertingGENERAL DESCRIPTION jitter-free output signals.The 74HC/HCT7540 are high-speed Si-gate CMOS The “75 ..
74HCT75D ,Quad bistable transparent latch
74HCT75D ,Quad bistable transparent latch
74HCT75D ,Quad bistable transparent latch
75321D , 20A, 55V, 0.036 Ohm, N-Channel UltraFET Power MOSFETs
75321D , 20A, 55V, 0.036 Ohm, N-Channel UltraFET Power MOSFETs
7555IBA , General Purpose Timers
7555IBA , General Purpose Timers
7555IBAZ , General Purpose Timers
7555IPA , General Purpose Timers

74HC74N-74HC74PW-74HCT74PW
Dual D-type flip-flop with set and reset; positive-edge trigger
1. General description
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have
individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary
nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time
requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at
the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to
slower clock rise and fall times. Inputs include clamp diodes that enable the use of current
limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits Input levels: For 74HC74: CMOS level For 74HCT74: TTL level Symmetrical output impedance Low power dissipation High noise immunity Balanced propagation delays Specified in compliance with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125C
3. Ordering information
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Rev. 4 — 27 August 2012 Product data sheet
Table 1. Ordering information
74HC74N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT74N
74HC74D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HCT74D
74HC74DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT337-1
74HCT74DB
NXP Semiconductors 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
4. Functional diagram
74HC74PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74HCT74PW
74HC74BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.53 0.85 mm
SOT762-1
74HCT74BQ
Table 1. Ordering information …continued
NXP Semiconductors 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description
1RD 1 asynchronous reset-direct input (active LOW) 2 data input
1CP 3 clock input (LOW-to-HIGH, edge-triggered)
1SD 4 asynchronous set-direct input (active LOW) 5 output 6 complement output
GND 7 ground (0 V) 8 complement output 9 output
2SD 10 asynchronous set-direct input (active LOW)
2CP 11 clock input (LOW-to-HIGH, edge-triggered) 12 data input
2RD 13 asynchronous reset-direct input (active LOW)
VCC 14 supply voltage
NXP Semiconductors 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
6. Functional description
[1] H= HIGH voltage level; L= LOW voltage level; X= don’t care.
[1] H= HIGH voltage level; L= LOW voltage level; = LOW-to-HIGH transition; Qn+1= state after the next LOW-to-HIGH CP transition; = don’t care.
7. Limiting values
[1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60C.
Table 3. Function table[1] H XXH L L XXL H L XXH H
Table 4. Function table[1]  LLH  HHL
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V - 20 mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V - 20 mA output current VO = 0.5 V to (VCC +0.5V) - 25 mA
ICC supply current - +100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation DIP14 package [1]- 750 mW
SO14, (T)SSOP14 and DHVQFN14
packages
[1]- 500 mW
NXP Semiconductors 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
8. Recommended operating conditions
9. Static characteristics
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC74
VIH HIGH-level
input voltage
VCC= 2.0V 1.5 1.2 - 1.5 - V
VCC= 4.5V 3.15 2.4 - 3.15 - V
VCC= 6.0V 4.2 3.2 - 4.2 - V
VIL LOW-level
input voltage
VCC= 2.0V - 0.8 0.5 - 0.5 V
VCC= 4.5V - 2.1 1.35 - 1.35 V
VCC= 6.0V - 2.8 1.8 - 1.8 V
VOH HIGH-level
output voltage =VIHorVIL= 4.0 mA; VCC= 4.5V 3.84 4.32 - 3.7 - V= 5.2 mA; VCC= 6.0V 5.34 5.81 - 5.2 - V
VOL LOW-level
output voltage =VIHorVIL =4.0 mA; VCC= 4.5V - 0.15 0.33 - 0.4 V =5.2 mA; VCC= 6.0V - 0.16 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =6.0V 1.0 - 1.0 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =6.0V 40 - 80 A input
capacitance
3.5 pF
74HCT74
VIH HIGH-level
input voltage
VCC= 4.5 V to 5.5V 2.0 1.6 - 2.0 - V
VIL LOW-level
input voltage
VCC= 4.5 V to 5.5V - 1.2 0.8 - 0.8 V
NXP Semiconductors 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
[1] All typical values are measured at Tamb =25C.
VOH HIGH-level
output voltage =VIHor VIL; VCC =4.5V=4 mA 3.84 4.32 - 3.7 - V
VOL LOW-level
output voltage =VIHor VIL; VCC =4.5V= 4.0 mA - 0.15 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =5.5V 1.0 - 1.0 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =5.5V 40 - 80 A
ICC additional
supply current =VCC 2.1V;
other inputs at VCCor GND;
VCC= 4.5Vto 5.5V; =0A
per input pin; nD, nRD
inputs 70 315 - 343 A
per input pin; nSD, nCP
input 80 360 - 392 A input
capacitance
3.5 pF
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
10. Dynamic characteristicsTable 8. Dynamic characteristics
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure9.
74HC74
tpd propagation
delay
nCP to nQ, nQ; see
Figure7
[2]
VCC = 2.0 V - 47 220 - 265 ns
VCC = 4.5 V - 17 44 - 53 ns
VCC =5V; CL =15pF - 14 - - - ns
VCC = 6.0 V - 14 37 - 45 ns
nSD to nQ, nQ; see
Figure8
[2]
VCC = 2.0 V - 50 250 - 300 ns
VCC = 4.5 V - 18 50 - 60 ns
VCC =5V; CL =15pF - 15 - - - ns
VCC = 6.0 V - 14 43 - 51 ns
nRD to nQ, nQ; see
Figure8
[2]
VCC = 2.0 V - 52 250 - 300 ns
VCC = 4.5 V - 19 50 - 60 ns
VCC =5V; CL =15pF - 16 - - - ns
VCC = 6.0 V - 15 43 - 51 ns transition
time
nQ, nQ; see Figure7 [3]
VCC = 2.0 V - 19 95 - 110 ns
VCC = 4.5 V - 7 19 - 22 ns
VCC = 6.0 V - 6 16 - 19 ns pulse width nCP HIGH or LOW;
see Figure7
VCC = 2.0 V 100 19 - 120 - ns
VCC = 4.5 V 20 7 - 24 - ns
VCC = 6.0 V 17 6 - 20 - ns
nSD, nRD LOW;
see Figure8
VCC = 2.0 V 100 19 - 120 - ns
VCC = 4.5 V 20 7 - 24 - ns
VCC = 6.0 V 17 6 - 20 - ns
trec recovery
time
nSD, nRD; see Figure8
VCC = 2.0 V 40 3 - 45 - ns
VCC = 4.5 V 8 1 - 9 - ns
VCC = 6.0 V 7 1 - 8 - ns
NXP Semiconductors 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
tsu set-up time nD to nCP; see Figure7
VCC = 2.0 V 75 6 - 90 - ns
VCC = 4.5 V 15 2 - 18 - ns
VCC = 6.0 V 13 2 - 15 - ns hold time nD to nCP; see Figure7
VCC = 2.0 V 3 6- 3 - ns
VCC = 4.5 V 3 2- 3 - ns
VCC = 6.0 V 3 2- 3 - ns
fmax maximum
frequency
nCP; see Figure7
VCC = 2.0 V 4.8 23 - 4.0 - MHz
VCC = 4.5 V 24 69 - 20 - MHz
VCC =5V; CL =15pF - 76 - - - MHz
VCC = 6.0 V 28 82 - 24 - MHz
CPD power
dissipation
capacitance =50pF;f= 1 MHz; =GNDto VCC
[4] -24 - - - pF
74HCT74
tpd propagation
delay
nCP to nQ, nQ; see
Figure7
[2]
VCC = 4.5 V - 18 44 - 53 ns
VCC =5V; CL =15pF - 15 - - - ns
nSD to nQ, nQ; see
Figure8
[2]
VCC = 4.5 V - 23 50 - 60 ns
VCC =5V; CL =15pF - 18 - - - ns
nRD to nQ, nQ; see
Figure8
[2]
VCC = 4.5 V - 24 50 - 60 ns
VCC =5V; CL =15pF - 18 - - - ns transition
time
nQ, nQ; see Figure7 [3]
VCC = 4.5 V - 7 19 - 22 ns pulse width nCP HIGH or LOW;
see Figure7
VCC = 4.5 V 23 9 - 27 - ns
nSD, nRD LOW;
see Figure8
VCC = 4.5 V 20 9 - 24 - ns
trec recovery
time
nSD, nRD; see Figure8
VCC = 4.5 V 8 1 - 9 - ns
tsu set-up time nD to nCP; see Figure7
VCC = 4.5 V 15 5 - 18 - ns
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure9.
NXP Semiconductors 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
[1] All typical values are measured at Tamb =25C.
[2] tpd is the same as tPLH and tPHL.
[3] tt is the same as tTHL and tTLH.
[4] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC = supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs. hold time nD to nCP; see Figure7
VCC = 4.5 V 3 3- 3 - ns
fmax maximum
frequency
nCP; see Figure7
VCC = 4.5 V 22 54 - 18 - MHz
VCC =5V; CL =15pF - 59 - - - MHz
CPD power
dissipation
capacitance =50pF;f= 1 MHz; =GNDto VCC - 1.5 V
[4] -29 - - - pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure9.
NXP Semiconductors 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
11. Waveforms
NXP Semiconductors 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Table 9. Measurement points
74HC74 0.5VCC 0.5VCC
74HCT74 1.3V 1.3V

Partno	Mfg	Dc	Qty	Available	Descript
74HC74N	TI	N/a	3862	avai	Dual D-type flip-flop with set and reset; positive-edge trigger
74HC74PW	PH	N/a	2502	avai	Dual D-type flip-flop with set and reset; positive-edge trigger
74HCT74PW	NXP	N/a	13368	avai	Dual D-type flip-flop with set and reset; positive-edge trigger