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74HC74
74HC74 Data Sheet
74HC74
Dual D Flip−Flop with Set
and Reset
High−Performance Silicon−Gate CMOSThe 74HC74 is identical in pinout to the LS74. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip−flop. The Set
and Reset inputs are asynchronous.
Features Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating V oltage Range: 2.0 to 6.0 V Low Input Current: 1.0 �A High Noise Immunity Characteristic of CMOS Devices In Compliance with the JEDEC Standard No. 7A Requirements ESD Performance: HBM � 2000 V; Machine Model � 200 V Chip Complexity: 128 FETs or 32 Equivalent Gates Pb−Free Packages are Available
