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74HC73D
Dual JK flip-flop with reset; negative-edge trigger
General descriptionThe 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC
standard no. 7A.
The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock
(nCP) and reset (nR) inputs; also complementary nQ and nQ outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock
transition for predictable operation.
The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock
and data inputs, forcing the nQ output LOW and the nQ output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: HBM EIA/JESD22-A114-B exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V. Multiple package options Specified from −40 °Cto+80 °C and from −40°Cto +125 °C.
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Philips Semiconductors 74HC73 Quick reference data[1] CPD is used to determine the dynamic power dissipation (PD in μW). =CPD× VCC2×fi× N+ ∑(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
∑(CL× VCC2×fo) = sum of outputs.
Ordering information
Table 1: Quick reference dataGND= 0 V; Tamb =25 °C; tr =tf= 6 ns.
tPHL, tPLH propagation delay CL= 15 pF; VCC =5 V - -
nCP to nQ - 16 - ns
nCP to nQ - 16 - ns
nR to nQ, nQ - 15 - ns
fmax maximum clock
frequency= 15 pF; VCC= 5 V - 77 - MHz input capacitance - 3.5 - pF
CPD power dissipation
capacitance per flip-flop= GND to VCC [1] -30 - pF
Table 2: Ordering information74HC73N −40 °C to +125°C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC73D −40 °C to +125°C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HC73DB −40 °C to +125°C SSOP14 plastic shrink small outline package; 14 leads; body width
5.3 mm
SOT337-1
74HC73PW −40 °C to +125°C TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
SOT402-1
Philips Semiconductors 74HC73 Functional diagram
Philips Semiconductors 74HC73 Pinning information
6.1 Pinning
6.2 Pin description
Table 3: Pin description1CP 1 clock input for flip-flop 1 (HIGH-to-LOW, edge-triggered) 2 asynchronous reset input for flip-flop 1 (active LOW) 3 synchronous K input for flip-flop 1
VCC 4 positive supply voltage
2CP 5 clock input for flip-flop 2 (HIGH-to-LOW, edge-triggered) 6 asynchronous reset input for flip-flop 2 (active LOW) 7 synchronous J input for flip-flop 2 8 complement flip-flop 2 output 9 true flip-flop 2 output 10 synchronous K input for flip-flop 2
Philips Semiconductors 74HC73 Functional description
7.1 Function table[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW CP transition;
X = don’t care;
↓ = HIGH-to-LOW CP transition.
Limiting values[1] Above 70 °C: Ptot derates linearly with 12 mW/K.
[2] Above 70 °C: Ptot derates linearly with 8 mW/K.
GND 11 ground (0 V) 12 true flip-flop 1 output 13 complement flip-flop 1 output 14 synchronous J input for flip-flop 1
Table 3: Pin description …continued
Table 4: Function table[1] X X X L H asynchronous reset ↓ hh q q toggle h L H load 0 (reset) l H L load 1 (set)
llq q hold (no change)
Table 5: Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
VCC supply voltage −0.5 +7 V
IIK input diode current VI < −0.5 V or VI >VCC+ 0.5 V - ±20 mA
IOK output diode current VO< −0.5 V or VO >VCC+ 0.5V - ±20 mA output source or sink
current
VO = −0.5 V to VCC+ 0.5V - ±25 mA
ICC, IGND VCC or GND current - ±50 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation
DIP14 package [1]- 750 mW
SO14, SSOP14 and
TSSOP14 packages
[2]- 500 mW
Philips Semiconductors 74HC73 Recommended operating conditions
10. Static characteristics
Table 6: Recommended operating conditionsVCC supply voltage 2.0 5.0 6.0 V input voltage 0 - VCC V output voltage 0 - VCC V
tr, tf input rise and fall
times except for
nCP
VCC = 2.0 V - - 1000 ns
VCC = 4.5 V - 6.0 500 ns
VCC = 6.0 V - - 400 ns
Tamb ambient
temperature
−40 - +125 °C
Table 7: Static characteristicsAt recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb =25°C
VIH HIGH-level input voltage VCC= 2.0V 1.5 1.2 - V
VCC= 4.5V 3.15 2.4 - V
VCC= 6.0V 4.2 3.2 - V
VIL LOW-level input voltage VCC= 2.0V - 0.8 0.5 V
VCC= 4.5V - 2.1 1.35 V
VCC= 6.0V - 2.8 1.8 V
VOH HIGH-level output voltage VI =VIHorVIL= −20 μA; VCC= 2.0V 1.9 2.0 - V= −20 μA; VCC= 4.5V 4.4 4.5 - V= −20 μA; VCC= 6.0V 5.9 6.0 - V=−4 mA; VCC= 4.5V 3.98 4.32 - V= −5.2 mA; VCC= 6.0V 5.48 5.81 - V
VOL LOW-level output voltage VI =VIHorVIL =20 μA; VCC= 2.0V - 0 0.1 V =20 μA; VCC= 4.5V - 0 0.1 V =20 μA; VCC= 6.0V - 0 0.1 V=4 mA; VCC= 4.5V - 0.15 0.26 V= 5.2 mA; VCC= 6.0V - 0.16 0.26 V
ILI input leakage current VI =VCCor GND; VCC= 6.0V - - ±0.1 μA
ICC quiescent supply current VI =VCCor GND; IO=0 A; VCC= 6.0V - - 4.0 μA input capacitance - 3.5 - pF
Philips Semiconductors 74HC73
Tamb= −40 °C to +85°C
VIH HIGH-level input voltage VCC= 2.0V 1.5 - - V
VCC= 4.5V 3.15 - - V
VCC= 6.0V 4.2 - - V
VIL LOW-level input voltage VCC= 2.0V - - 0.5 V
VCC= 4.5V - - 1.35 V
VCC= 6.0V - - 1.8 V
VOH HIGH-level output voltage VI =VIHorVIL= −20 μA; VCC= 2.0V 1.9 - - V= −20 μA; VCC= 4.5V 4.4 - - V= −20 μA; VCC= 6.0V 5.9 - - V=−4 mA; VCC= 4.5V 3.84 - - V= −5.2 mA; VCC= 6.0V 5.34 - - V
VOL LOW-level output voltage VI =VIHorVIL =20 μA; VCC= 2.0V - - 0.1 V =20 μA; VCC= 4.5V - - 0.1 V =20 μA; VCC= 6.0V - - 0.1 V=4 mA; VCC= 4.5V - - 0.33 V= 5.2 mA; VCC= 6.0V - - 0.33 V
ILI input leakage current VI =VCCor GND; VCC= 6.0V - - ±1.0 μA
ICC quiescent supply current VI =VCCor GND; IO=0 A; VCC= 6.0V - - 40.0 μA
Table 7: Static characteristics …continuedAt recommended operating conditions; voltages are referenced to GND (ground=0V).
Philips Semiconductors 74HC73
Tamb= −40 °C to +125°C
VIH HIGH-level input voltage VCC= 2.0V 1.5 - - V
VCC= 4.5V 3.15 - - V
VCC= 6.0V 4.2 - - V
VIL LOW-level input voltage VCC= 2.0V - - 0.5 V
VCC= 4.5V - - 1.35 V
VCC= 6.0V - - 1.8 V
VOH HIGH-level output voltage VI =VIHorVIL= −20 μA; VCC= 2.0V 1.9 - - V= −20 μA; VCC= 4.5V 4.4 - - V= −20 μA; VCC= 6.0V 5.9 - - V=−4 mA; VCC= 4.5V 3.7 - - V= −5.2 mA; VCC= 6.0V 5.2 - - V
VOL LOW-level output voltage VI =VIHorVIL =20 μA; VCC= 2.0V - - 0.1 V =20 μA; VCC= 4.5V - - 0.1 V =20 μA; VCC= 6.0V - - 0.1 V=4 mA; VCC= 4.5V - - 0.4 V= 5.2 mA; VCC= 6.0V - - 0.4 V
ILI input leakage current VI =VCCor GND; VCC= 6.0V - - ±1.0 μA
ICC quiescent supply current VI =VCCor GND; IO=0 A; VCC= 6.0V - - 80.0 μA
Table 7: Static characteristics …continuedAt recommended operating conditions; voltages are referenced to GND (ground=0V).
Philips Semiconductors 74HC73
11. Dynamic characteristics
Table 8: Dynamic characteristicsGND= 0 V; tr=tf= 6 ns; CL= 50 pF; see Figure8.
Tamb = 25°C
tPHL, tPLH propagation delay nCP to nQ see Figure6
VCC = 2.0 V - 52 160 ns
VCC = 4.5 V - 19 32 ns
VCC = 6.0 V - 15 27 ns
VCC= 5.0 V; CL =15pF - 16 - ns
propagation delay nCP to nQ see Figure6
VCC = 2.0 V - 52 160 ns
VCC = 4.5 V - 19 32 ns
VCC = 6.0 V - 15 27 ns
VCC= 5.0 V; CL =15pF - 16 - ns
propagation delay nR to nQ, nQ see Figure7
VCC = 2.0 V - 50 145 ns
VCC = 4.5 V - 18 29 ns
VCC = 6.0 V - 14 25 ns
VCC= 5.0 V; CL =15pF - 15 - ns
tTHL, tTLH output transition time see Figure6
VCC = 2.0 V - 19 75 ns
VCC = 4.5 V - 7 15 ns
VCC = 6.0 V - 6 13 ns nCP clock pulse width HIGH or LOW see Figure6
VCC = 2.0 V 80 22 - ns
VCC = 4.5 V 16 8 - ns
VCC = 6.0 V 14 6 - ns
nR reset pulse width HIGH or LOW see Figure7
VCC = 2.0 V 80 22 - ns
VCC = 4.5 V 16 8 - ns
VCC = 6.0 V 14 6 - ns
trem removal time nR to nCP see Figure7
VCC = 2.0 V 80 22 - ns
VCC = 4.5 V 16 8 - ns
VCC = 6.0 V 14 6 - ns
tsu set-up time nJ, nK to nCP see Figure6
VCC = 2.0 V 80 22 - ns
VCC = 4.5 V 16 8 - ns
VCC = 6.0 V 14 6 - ns
Philips Semiconductors 74HC73 hold time nJ, nK to nCP see Figure6
VCC = 2.0 V 3 −8- ns
VCC = 4.5 V 3 −3- ns
VCC = 6.0 V 3 −2- ns
fmax maximum clock frequency see Figure6
VCC = 2.0 V 6.0 23 - MHz
VCC = 4.5 V 30 70 - MHz
VCC = 6.0 V 35 83 - MHz
VCC= 5.0 V; CL=15pF - 77 - MHz
CPD power dissipation capacitance per
flip-flop= GND to VCC [1] -30 - pF
Tamb = −40 °C to +85°C
tPHL, tPLH propagation delay nCP to nQ see Figure6
VCC = 2.0 V - - 200 ns
VCC = 4.5 V - - 40 ns
VCC = 6.0 V - - 34 ns
propagation delay nCP to nQ see Figure6
VCC = 2.0 V - - 200 ns
VCC = 4.5 V - - 40 ns
VCC = 6.0 V - - 34 ns
propagation delay nR to nQ, nQ see Figure7
VCC = 2.0 V - - 180 ns
VCC = 4.5 V - - 36 ns
VCC = 6.0 V - - 31 ns
tTHL, tTLH output transition time see Figure6
VCC = 2.0 V - - 95 ns
VCC = 4.5 V - - 19 ns
VCC = 6.0 V - - 16 ns nCP clock pulse width HIGH or LOW see Figure6
VCC = 2.0 V 100 - - ns
VCC = 4.5 V 20 - - ns
VCC = 6.0 V 17 - - ns
nR reset pulse width HIGH or LOW see Figure7
VCC = 2.0 V 100 - - ns
VCC = 4.5 V 20 - - ns
VCC = 6.0 V 17 - - ns
trem removal time nR to nCP see Figure7
VCC = 2.0 V 100 - - ns
VCC = 4.5 V 20 - - ns
VCC = 6.0 V 17 - - ns
Table 8: Dynamic characteristics …continuedGND= 0 V; tr=tf= 6 ns; CL= 50 pF; see Figure8.
Philips Semiconductors 74HC73tsu set-up time nJ, nK to nCP see Figure6
VCC = 2.0 V 100 - - ns
VCC = 4.5 V 20 - - ns
VCC = 6.0 V 17 - - ns hold time nJ, nK to nCP see Figure6
VCC = 2.0 V 3 - - ns
VCC = 4.5 V 3 - - ns
VCC = 6.0 V 3 - - ns
fmax maximum clock frequency see Figure6
VCC = 2.0 V 4.8 - - MHz
VCC = 4.5 V 24 - - MHz
VCC = 6.0 V 28 - - MHz
Tamb = −40 °C to +125°C
tPHL, tPLH propagation delay nCP to nQ see Figure6
VCC = 2.0 V - - 240 ns
VCC = 4.5 V - - 48 ns
VCC = 6.0 V - - 41 ns
propagation delay nCP to nQ see Figure6
VCC = 2.0 V - - 240 ns
VCC = 4.5 V - - 48 ns
VCC = 6.0 V - - 41 ns
propagation delay nR to nQ, nQ see Figure7
VCC = 2.0 V - - 220 ns
VCC = 4.5 V - - 44 ns
VCC = 6.0 V - - 38 ns
tTHL, tTLH output transition time see Figure6
VCC = 2.0 V - - 110 ns
VCC = 4.5 V - - 22 ns
VCC = 6.0 V - - 19 ns nCP clock pulse width HIGH or LOW see Figure6
VCC = 2.0 V 120 - - ns
VCC = 4.5 V 24 - - ns
VCC = 6.0 V 20 - - ns
nR reset pulse width HIGH or LOW see Figure7
VCC = 2.0 V 120 - - ns
VCC = 4.5 V 24 - - ns
VCC = 6.0 V 20 - - ns
Table 8: Dynamic characteristics …continuedGND= 0 V; tr=tf= 6 ns; CL= 50 pF; see Figure8.
