74HC670D ,4 x 4 register file; 3-stateGENERAL DESCRIPTION(R and R ). The addressed word appears at the fourA BThe 74HC/HCT670 are high-sp ..
74HC670D ,4 x 4 register file; 3-stateFEATURES the location of the stored word. When the WE input isLOW, the data is entered into the add ..
74HC670N ,74HC/HCT670; 4 x 4 register file; 3-stateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC688D ,8-bit magnitude comparatorINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC688N ,74HC/HCT688; 8-bit magnitude comparatorINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC688N ,74HC/HCT688; 8-bit magnitude comparatorINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74S241 ,Octal 3-State Buffer / Line Driver / Line ReceiverFeatures I Typical power dissipation (enabled)
. . . Inverting 450 mW
I 3-STATE outputs drive bus ..
74SSTUB32868AZRHR ,28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA -40 to 85These devices have limited built-in ESD protection. The leads should be shorted together or the dev ..
74SSTUB32868ZRHR ,28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA -40 to 85These devices have limited built-in ESD protection. The leads should be shorted together or the dev ..
74SSTV16859DGGRG4 ,13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 64-TSSOP 0 to 70logic diagram (positive logic)51RESET48CLK49CLK45VREFOne of 13 channels35D1 16Q1A1DC132RQ1BTo 12 Ot ..
74SSTVF32852ZKFR ,24-Bit to 48-Bit Registered Buffer with SSTL_2 Inputs and OutputsSN74SSTVF32852 24-BIT TO 48-BIT REGISTERED BUFFERWITH SSTL_2 INPUTS AND OUTPUTSSCES426A – FEBRUARY ..
74TVC16222ADGGRG4 ,22-Bit Voltage Clamp 48-TSSOP -40 to 85maximum ratings over operating free-air temperature range (unless otherwise noted)Input voltage ran ..
74HC670D-74HC670N-74HCT670D-74HCT670N
74HC/HCT670; 4 x 4 register file; 3-state
Philips Semiconductors Product specification
4 x 4 register file; 3-state 74HC/HCT670
FEATURES Simultaneous and independent read and write
operations Expandable to almost any word size and bit length Output capability: bus driver ICC category: MSI
GENERAL DESCRIPTIONThe 74HC/HCT670 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT670 are 16-bit 3-state register files
organized as 4 words of 4 bits each. Separated read and
write address inputs (RA, RB and WA,WB) and enable
inputs (RE andWE) are available, permitting simultaneous
writing into one word location and reading from another
location. The 4-bit word to be stored is presented to four
data inputs (D0 to D3). The WA and WB inputs determine
the location of the stored word. When the WE input is
LOW, the data is entered into the addressed location. The
addressed location remains transparent to the data while
the WE input is LOW. Data supplied at the inputs will be
read out in true (non-inverting) form from the 3-state
outputs (Q0 to Q3). Dn and Wn inputs are inhibited when is HIGH.
Direct acquisition of data stored in any of the four registers
is made possible by individual read address inputs
(RA and RB). The addressed word appears at the four
outputs when the RE is LOW. Data outputs are in the high
impedance OFF-state when RE is HIGH. This permits
outputs to be tied together to increase the word capacity to
very large numbers.
Design of the read enable signals for the stacked devices
must ensure that there is no overlap in the LOW levels
which would cause more than one output to be active at
the same time. Parallel expansion to generate n-bit words
is accomplished by driving the enable and address inputs
of each device in parallel.
QUICK REFERENCE DATAGND=0 V; Tamb =25 °C; tr =tf= 6 ns
Notes CPD is used to determine the dynamic power dissipation (PD in μW): =CPD× VCC2×fi +∑ (CL× VCC2×fo) where:= input frequency in MHz= output frequency in MHz (CL× VCC2×fo)= sum of outputs= output load capacitance in pF
VCC= supply voltage in V For HC the condition is VI= GND to VCC;
for HCT the condition is VI= GND to VCC −1.5V
ORDERING INFORMATIONSee “74HC/HCT/HCU/HCMOS Logic Package Information”.
Philips Semiconductors Product specification
4 x 4 register file; 3-state 74HC/HCT670
PIN DESCRIPTION
WRITE MODE SELECT TABLE
Note The write address (WA and WB) to the
“internal latches” must be stable while WEis
LOW for conventional operation.
READ MODE SELECT TABLE
Notes The selection of the “internal latches” by read address
(RA and RB) are not constrained by WE or RE operation.= HIGH voltage level= LOW voltage level
Philips Semiconductors Product specification
4 x 4 register file; 3-state 74HC/HCT670
Philips Semiconductors Product specification
4 x 4 register file; 3-state 74HC/HCT670
DC CHARACTERISTICS FOR 74HCFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HCGND=0 V; tr =tf=6 ns; CL =50pF
Philips Semiconductors Product specification
4 x 4 register file; 3-state 74HC/HCT670
DC CHARACTERISTICS FOR 74HCTFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT typesThe value of additional quiescent supply current (ΔICC) for a unit load of 1 is given in the family specifications.
To determine ΔICC per input, multiply this value by the unit load coefficient shown in the table below.
