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74HC652D-74HC652N-74HCT652D-74HCT652N
Octal bus transceiver/register; 3-state
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
FEATURES Multiplexed real-time and stored
data Independent register for A and B
buses Independent enables for A and B
buses 3-state Output capability: Bus driver Low power consumption by CMOS
technology ICC category: MSI.
APPLICATIONS Bus interfaces.
DESCRIPTIONThe 74HC/HCT652 are high-speed
SI-gate CMOS devices and are pin
compatible with Low power Schottky
TTL (LSTTL). They are specified in
compliance with Jedec standard
no. 7A.
The 74HC/HCT652 consist of 8
non-inverting bus transceiver circuits
with 3-state outputs, D-type flip-flops
and central circuitry arranged for
multiplexed transmission of data
directly from the data bus or from the
internal storage registers. Data on the
“A” or “B” or both buses, will be stored
in the internal registers, at the
appropriate clock pins (CPAB or
CPBA) regardless of the select pins
(SAB and SBA) or output enable (OEAB
and OEBA) control pins. Depending
on the select inputs SAB and SBA data
can directly go from input to output
(real time mode) or data can be
controlled by the clock (storage
mode), this is when the output enable
pins this operating mode permits. The
output enable pins OEAB and OEBA
determine the operation mode of the
transceiver. When OEAB is LOW, no
data transmission from An to Bnis
possible and when OEBA is HIGH,
there is no data transmission from Bn
to Anpossible. When SAB and SBA are
in the real time transfer mode, it is
also possible to store data without
using the internal D-type flip-flops by
simultaneously enabling OEAB and
OEBA. In this configuration each
output reinforces its input. Thus when
all other data sources to the two sets
of bus lines are at high-impedance,
each set of the bus lines will remain at
its last state. This type differs from the
HC/HCT646 in one extra
bus-management function. This is the
possibility to transfer stored “A data to
the “B” bus and transfer stored ”B”
data to the ”A” bus at the same time.
The examples at the application
information demonstrate all bus
management functions.
Schmitt-trigger action in the clock
inputs makes the circuit highly
tolerant to slower clock rise and fall
times.
QUICK REFERENCE DATAGND= 0 V; Tamb =25°C; tr =tf= 6 ns; VCC= 4.5 V; CL= 50 pF.
Notes CPD is used to determine the dynamic power dissipation (PD in μW): =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:= input frequency in MHz; CL= output load capacitance in pF;= output frequency in MHz; VCC= supply voltage in V;
∑ (CL × VCC2 × fo)= sum of the outputs
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
ORDERING AND PACKAGE INFORMATION
PINNING
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
FUNCTION TABLE
Notes H= HIGH voltage level= LOW voltage level= don’t care= LOW-to-HIGH transition The data output functions may be enabled or disabled by various signals at OEAB and OEBA inputs. Data input
functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock
inputs.
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
DC CHARACTERISTICS FOR 74HCFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI.
AC CHARACTERISTICS FOR 74HCGND= 0 V; tr =tf= 6 ns; CL= 50 pF.
