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74HC597N-74HC597PW
8-bit shift register with input flip-flops
1. General descriptionThe 74HC597; 74HCT597 is an 8-bit shift register with input flip-flops. It consists of an
8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage
register and the shift register have positive edge-triggered clocks. The shift register also
has direct load (from storage) and clear inputs. Inputs include clamp diodes that enable
the use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits Complies with JEDEC standard JESD7A Input levels: For 74HC597: CMOS level For 74HCT597: TTL level 8-bit parallel storage register inputs Shift register has direct overriding load and clear ESD protection: HBM EIA/JESD22-A114F exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V Specified from 40 Cto+85 C and from 40 Cto+125C Multiple package options
3. Ordering information
74HC597; 74HCT597
8-bit shift register with input flip-flops
Rev. 3 — 15 April 2014 Product data sheet
Table 1. Ordering information
NXP Semiconductors 74HC597; 74HCT597
8-bit shift register with input flip-flops
4. Functional diagramNXP Semiconductors 74HC597; 74HCT597
8-bit shift register with input flip-flopsNXP Semiconductors 74HC597; 74HCT597
8-bit shift register with input flip-flops
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description
NXP Semiconductors 74HC597; 74HCT597
8-bit shift register with input flip-flops
6. Functional description[1] H = HIGH voltage level.
L = LOW voltage level.
X = don’t care.
= positive-going transition.
Table 3. Function table[1]
NXP Semiconductors 74HC597; 74HCT597
8-bit shift register with input flip-flops
7. Limiting values[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70C.
[2] For SO16: Ptot derates linearly with 8 mW/K above 70C.
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60C.
8. Recommended operating conditions
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0V)
NXP Semiconductors 74HC597; 74HCT597
8-bit shift register with input flip-flops
9. Static characteristicsTable 6. Static characteristicsAt recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC597; 74HCT597
8-bit shift register with input flip-flops
10. Dynamic characteristics
Table 6. Static characteristics …continuedAt recommended operating conditions; voltages are referenced to GND (ground=0V).
Table 7. Dynamic characteristicsVoltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 14.
NXP Semiconductors 74HC597; 74HCT597
8-bit shift register with input flip-flops
Table 7. Dynamic characteristics …continuedVoltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 14.
NXP Semiconductors 74HC597; 74HCT597
8-bit shift register with input flip-flops
Table 7. Dynamic characteristics …continuedVoltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 14.
NXP Semiconductors 74HC597; 74HCT597
8-bit shift register with input flip-flops
Table 7. Dynamic characteristics …continuedVoltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 14.
NXP Semiconductors 74HC597; 74HCT597
8-bit shift register with input flip-flops[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC = supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
11. Waveforms
Table 7. Dynamic characteristics …continuedVoltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 14.
