74HC595D.-74HCT595PW Fast Delivery |IC PHOENIX CO.,LIMITED

74HCT595PW ,8-bit serial-in, serial or parallel-out shift register with output latches; 3-stateApplications Serial-to-parallel data conversion Remote control holding register74HC595; 74HCT595N ..
74HCT597 ,8-bit shift register with input flip-flops
74HCT597D ,8-bit shift register with input flip-flopsGENERAL DESCRIPTION• 8-bit parallel storage register inputs The 74HC/HCT597 are high-speed Si-gate ..
74HCT597D ,8-bit shift register with input flip-flopsGENERAL DESCRIPTION• 8-bit parallel storage register inputs The 74HC/HCT597 are high-speed Si-gate ..
74HCT597N ,8-bit shift register with input flip-flopsGENERAL DESCRIPTION• 8-bit parallel storage register inputs The 74HC/HCT597 are high-speed Si-gate ..
74HCT597N ,8-bit shift register with input flip-flopsINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
75185L-R20-R , MULTIPLE RS-232 DRIVERS AND RECEIVERS
75232L-P20-R , MULTIPLE RS-232 DRIVERS AND RECEIVERS
75232L-R20-R , MULTIPLE RS-232 DRIVERS AND RECEIVERS
75321D , 20A, 55V, 0.036 Ohm, N-Channel UltraFET Power MOSFETs
75321D , 20A, 55V, 0.036 Ohm, N-Channel UltraFET Power MOSFETs
7555IBA , General Purpose Timers

74HC595D.-74HCT595PW
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
1. General description
The 74HC595; 74HCT595 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard No. 7A.
The 74HC595; 74HCT595 are 8-stage serial shift registers with a storage register and
3-state outputs. The registers have separate clocks.
Data is shifted on the positive-going transitions of the shift register clock input (SHCP).
The data in each register is transferred to the storage register on a positive-going
transition of the storage register clock input (STCP). If both clocks are connected together,
the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.
It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The
storage register has 8 parallel 3-state bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW.
2. Features and benefits 8-bit serial input 8-bit serial or parallel output Storage register with 3-state outputs Shift register with direct clear 100 MHz (typical) shift out frequency ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Specified from 40 C to +85 C and from 40 C to +125C
3. Applications Serial-to-parallel data conversion Remote control holding register
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Rev. 6 — 12 December 2011 Product data sheet
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;3-state
4. Ordering information
5. Functional diagram
Table 1. Ordering information
74HC595N 40 C to +125C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT595N
74HC595D 40 C to +125C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HCT595D
74HC595DB 40 C to +125C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HCT595DB
74HC595PW 40 C to +125C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT595PW
74HC595BQ 40 C to +125C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5  3.5  0.85 mm
SOT763-1
74HCT595BQ
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;3-state
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;3-state
6. Pinning information
6.1 Pinning
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;3-state
6.2 Pin description
7. Functional description
[1] H= HIGH voltage state;= LOW voltage state;= LOW-to-HIGH transition;= don’t care;= no change;= high-impedance OFF-state.
Table 2. Pin description 1 parallel data output 1 2 parallel data output 2 3 parallel data output 3 4 parallel data output 4 5 parallel data output 5 6 parallel data output 6 7 parallel data output 7
GND 8 ground (0 V)
Q7S 9 serial data output 10 master reset (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input 13 output enable input (active LOW) 14 serial data input 15 parallel data output 0
VCC 16 supply voltage
Table 3. Function table[1] X L L X L NC a LOW-level on MR only affects the shift registers  L L X L L empty shift register loaded into storage register X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).  L H X NC QnS contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages L H X Q6S QnS contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;3-state
8. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[3] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
[4] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC+ 0.5 V - 20 mA
IOK output clamping current VO< 0.5 V or VO > VCC + 0.5 V - 20 mA output current VO= 0.5 V to (VCC +0.5V)
pin Q7S - 25 mA
pins Qn - 35 mA
ICC supply current - 70 mA
IGND ground current 70 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation
DIP16 package [1]- 750 mW
SO16 package [2]- 500 mW
SSOP16 package [3]- 500 mW
TSSOP16 package [3]- 500 mW
DHVQFN16 package [4]- 500 mW
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;3-state
9. Recommended operating conditions
10. Static characteristics
Table 5. Recommended operating conditions
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
t/V input transition rise and
fall rate
VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC595
VIH HIGH-level
input voltage
VCC= 2.0V 1.5 1.2 - 1.5 - V
VCC= 4.5V 3.15 2.4 - 3.15 - V
VCC= 6.0V 4.2 3.2 - 4.2 - V
VIL LOW-level
input voltage
VCC= 2.0V - 0.8 0.5 - 0.5 V
VCC= 4.5V - 2.1 1.35 - 1.35 V
VCC= 6.0V - 2.8 1.8 - 1.8 V
VOH HIGH-level
output voltage =VIHorVIL
all outputs= 20 A; VCC= 2.0V 1.9 2.0 - 1.9 - V= 20 A; VCC= 4.5V 4.4 4.5 - 4.4 - V= 20 A; VCC= 6.0V 5.9 6.0 - 5.9 - V
Q7S output= 4mA; VCC= 4.5V 3.84 4.32 - 3.7 - V= 5.2 mA; VCC= 6.0V 5.34 5.81 - 5.2 - V
Qn bus driver outputs= 6mA; VCC= 4.5V 3.84 4.32 - 3.7 - V= 7.8 mA; VCC= 6.0V 5.34 5.81 - 5.2 - V
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;3-state
VOL LOW-level
output voltage =VIHorVIL
all outputs =20 A; VCC= 2.0V - 0 0.1 - 0.1 V =20 A; VCC= 4.5V - 0 0.1 - 0.1 V =20 A; VCC= 6.0V - 0 0.1 - 0.1 V
Q7S output =4mA; VCC= 4.5V - 0.15 0.33 - 0.4 V =5.2 mA; VCC= 6.0V - 0.16 0.33 - 0.4 V
Qn bus driver outputs =6mA; VCC= 4.5V - 0.15 0.33 - 0.4 V =7.8 mA; VCC= 6.0V - 0.16 0.33 - 0.4 V input leakage
current =VCCor GND; VCC =6.0V - - 1.0 - 1.0 A
IOZ OFF-state
output current =VIHor VIL; VCC =6.0V; =VCCor GND 5.0 - 10 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =6.0V - 80 - 160 A input
capacitance
-3.5 - - - pF
74HCT595
VIH HIGH-level
input voltage
VCC= 4.5 V to 5.5V 2.0 1.6 - 2.0 - V
VIL LOW-level
input voltage
VCC= 4.5 V to 5.5V - 1.2 0.8 - 0.8 V
VOH HIGH-level
output voltage =VIHor VIL; VCC =4.5V
all outputs= 20A 4.4 4.5 - 4.4 - V
Q7S output=4 mA 3.84 4.32 - 3.7 - V
Qn bus driver outputs=6 mA 3.7 4.32 - 3.7 - V
VOL LOW-level
output voltage =VIHor VIL; VCC =4.5V
all outputs =20A - 0 0.1 - 0.1 V
Q7S output= 4.0 mA - 0.15 0.33 - 0.4 V
Qn bus driver outputs= 6.0 mA - 0.16 0.33 - 0.4 V input leakage
current =VCCor GND; VCC =5.5V - - 1.0 - 1.0 A
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;3-state
IOZ OFF-state
output current =VIHor VIL; VCC =5.5 V; =VCCor GND 5.0 - 10 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =5.5V - 80 - 160 A
ICC additional
supply current
per input pin; IO =0A; VI =VCC
2.1 V; other inputs at VCCor GND;
VCC= 4.5Vto 5.5V
pins MR, SHCP, STCP, OE - 150 675 - 735 A
pin DS - 25 113 - 123 A input
capacitance
-3.5 - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;3-state
11. Dynamic characteristicsTable 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
74HC595
tpd propagation
delay
SHCPto Q7S; see Figure9 [2]
VCC = 2 V - 52 160 - 200 - 240 ns
VCC = 4.5 V - 19 32 - 40 - 48 ns
VCC = 6 V - 15 27 - 34 - 41 ns
STCPto Qn; see Figure10 [2]
VCC = 2 V - 55 175 - 220 - 265 ns
VCC = 4.5 V - 20 35 - 44 - 53 ns
VCC = 6 V - 16 30 - 37 - 45 nsto Q7S; see Figure12 [3]
VCC = 2 V - 47 175 - 220 - 265 ns
VCC = 4.5 V - 17 35 - 44 - 53 ns
VCC = 6 V - 14 30 - 37 - 45 ns
ten enable time OE to Qn; see Figure13 [4]
VCC = 2 V - 47 150 - 190 - 225 ns
VCC = 4.5 V - 17 30 - 38 - 45 ns
VCC = 6 V - 14 26 - 33 - 38 ns
tdis disable time OE to Qn; see Figure13 [5]
VCC = 2 V - 41 150 - 190 - 225 ns
VCC = 4.5 V - 15 30 - 38 - 45 ns
VCC = 6 V - 12 27 - 33 - 38 ns pulse width SHCP HIGH or LOW;
see Figure9
VCC = 2 V 75 17 - 95 - 110 - ns
VCC = 4.5 V 15 6 - 19 - 22 - ns
VCC = 6 V 13 5 - 16 - 19 - ns
STCP HIGH or LOW;
see Figure10
VCC = 2 V 75 11 - 95 - 110 - ns
VCC = 4.5 V 15 4 - 19 - 22 - ns
VCC = 6 V 13 3 - 16 - 19 - ns
MR LOW; see Figure12
VCC = 2 V 75 17 - 95 - 110 - ns
VCC = 4.5 V 15 6 - 19 - 22 - ns
VCC = 6 V 13 5 - 16 - 19 - ns
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;3-state
tsu set-up time DS to SHCP; see Figure10
VCC = 2 V 50 11 - 65 - 75 - ns
VCC = 4.5 V 10 4 - 13 - 15 - ns
VCC = 6 V 9 3 - 11 - 13 - ns
SHCP to STCP;
see Figure11
VCC = 2 V 75 22 - 95 - 110 - ns
VCC = 4.5 V 15 8 - 19 - 22 - ns
VCC = 6 V 13 7 - 16 - 19 - ns hold time DS to SHCP; see Figure11
VCC = 2 V 3 6- 3 - 3 - ns
VCC = 4.5 V 3 2- 3 - 3 - ns
VCC = 6 V 3 2- 3 - 3 - ns
trec recovery
time
MR to SHCP; see Figure12
VCC = 2 V 50 19 - 65 - 75 - ns
VCC = 4.5 V 10 7- 13 - 15 - ns
VCC = 6 V 9 6- 11 - 13 - ns
fmax maximum
frequency
SHCP or STCP;
see Figure 9 and 10
VCC = 2 V 9 30 - 4.8 - 4 - MHz
VCC = 4.5 V 30 91 - 24 - 20 - MHz
VCC = 6 V 35 108 - 28 - 24 - MHz
CPD power
dissipation
capacitance
fi = 1 MHz; VI =GNDto VCC [6][7] -115 - - - - - pF
74HCT595; VCC = 4.5 V to 5.5 V
tpd propagation
delay
SHCPto Q7S; see Figure9 [2] -25 42 - 53 - 63 ns
STCPto Qn; see Figure10 [2] -24 40 - 50 - 60 nsto Q7S; see Figure12 [3] -23 40 - 50 - 60 ns
ten enable time OE to Qn; see Figure13 [4] -21 35 - 44 - 53 ns
tdis disable time OE to Qn; see Figure13 [5] -18 30 - 38 - 45 ns pulse width SHCP HIGH or LOW;
see Figure9 6 - 20 - 24 - ns
STCP HIGH or LOW;
see Figure10 5 - 20 - 24 - ns
MR LOW; see Figure12 20 8 - 25 - 30 - ns
tsu set-up time DS to SHCP; see Figure10 16 5 - 20 - 24 - ns
SHCP to STCP;
see Figure11 8 - 20 - 24 - ns hold time DS to SHCP; see Figure11 3 2- 3 - 3 - ns
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;3-state
[1] Typical values are measured at nominal supply voltage.
[2] tpd is the same as tPHL and tPLH.
[3] tpd is the same as tPHL only.
[4] ten is the same as tPZL and tPZH.
[5] tdis is the same as tPLZ and tPHZ.
[6] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;
(CL VCC2fo)= sum of outputs;= output load capacitance inpF;
VCC= supply voltage inV.
[7] All 9 outputs switching.
12. Waveforms
trec recovery
time
MR to SHCP; see Figure12 10 7- 13 - 15 - ns
fmax maximum
frequency
SHCP and STCP;
see Figure 9 and 10 52 - 24 - 20 - MHz
CPD power
dissipation
capacitance
fi = 1 MHz; VI =GNDto VCC [6]
[7] - 130 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.

Partno	Mfg	Dc	Qty	Available	Descript
74HC595D. \|74HC595D	NXP	N/a	500	avai	8-bit serial-in/serial or parallel-out shift register with output latches; 3-state
74HCT595PW	NXP	N/a	12330	avai	8-bit serial-in, serial or parallel-out shift register with output latches; 3-state