74HC564N Fast Delivery |IC PHOENIX CO.,LIMITED

74HC564N ,Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
74HC564N ,Octal D-type flip-flop; positive-edge trigger; 3-state; invertingapplications. A clock (CP) and an outputenable (OE) input are common to all ﬂip-ﬂops.The 8 ﬂip-ﬂops ..
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74HC564N
Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
General descriptionThe 74HC564isa high-speed Si-gate CMOS device andis pin compatible with low-power
Schottky TTL (LSTTL). The 74HC564 is speciﬁed in compliance with JEDEC
standard no. 7A.
The 74HC564 is a octal D-type ﬂip-ﬂop featuring separate D-type inputs for each ﬂip-ﬂop
and inverting 3-state outputs for bus oriented applications. A clock (CP) and an output
enable (OE) input are common to all ﬂip-ﬂops.
The8 ﬂip-ﬂops will store the stateof their individual D-inputs that meet the set-up and hold
times requirementson the LOW-to-HIGH CP transition. When OEis LOW, the contentsof
the 8 ﬂip-ﬂops are available at the outputs. When OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input does not affect the state of the
ﬂip-ﬂops.
The 74HC564 is functionally identical to the 74HC574 but has inverting outputs. The
74HC564 is functionally identical to the 74HC534, but has a different pinning. Features 3-state inverting outputs for bus oriented applications 8-bit positive-edge triggered register Common 3-state output enable input Independent register and 3-state buffer operation Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: HBM EIA/JESD22-A114-B exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V. Multiple package options Speciﬁed from −40 °Cto+80 °C and from −40°Cto +125 °C.
74HC564
Octal D-type ﬂip-ﬂop; positive-edge trigger; 3-state; inverting
Philips Semiconductors 74HC564 Quick reference data
[1] CPD is used to determine the dynamic power dissipation (PD in μW). =CPD× VCC2×fi× N+ ∑(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
∑(CL× VCC2×fo) = sum of outputs. Ordering information
Table 1: Quick reference data
GND= 0 V; Tamb =25 °C; tr =tf= 6 ns.
tPHL, tPLH propagationdelayCPQn= 15 pF;
VCC =5 V
-15 - ns
fmax maximum clock
frequency= 15 pF;
VCC =5 V 127 - MHz input capacitance - 3.5 - pF
CPD power dissipation
capacitance per
ﬂip-ﬂop= GND to VCC [1] -27 - pF
Table 2: Ordering information
74HC564N −40 °C to +125°C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HC564D −40 °C to +125°C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
Philips Semiconductors 74HC564 Functional diagram
Philips Semiconductors 74HC564 Pinning information
6.1 Pinning
Philips Semiconductors 74HC564
6.2 Pin description Functional description
7.1 Function table
[1]H= HIGH voltage level;= HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;= LOW voltage level;= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;= high-impedance OFF-state;= LOW-to-HIGH clock transition.
Table 3: Pin description 1 3-state output enable input (active LOW) 2 data input 0 3 data input 1 4 data input 2 5 data input 3 6 data input 4 7 data input 5 8 data input 6 9 data input 7
GND 10 ground (0 V) 11 clock input (LOW-to-HIGH, edge-triggered) 12 3-state ﬂip-ﬂop output 7 13 3-state ﬂip-ﬂop output 6 14 3-state ﬂip-ﬂop output 5 15 3-state ﬂip-ﬂop output 4 16 3-state ﬂip-ﬂop output 3 17 3-state ﬂip-ﬂop output 2 18 3-state ﬂip-ﬂop output 1 19 3-state ﬂip-ﬂop output 0
VCC 20 positive supply voltage
Table 4: Function table[1]
Load and read
register ↑ lL H L
Load register and
disable output ↑ lL Z Z
Philips Semiconductors 74HC564 Limiting values
[1] Above 70 °C: Ptot derates linearly with 12 mW/K.
[2] Above 70 °C: Ptot derates linearly with 8 mW/K. Recommended operating conditions
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
VCC supply voltage −0.5 +7 V
IIK input diode current VI < −0.5 V or VI >VCC+ 0.5 V - ±20 mA
IOK output diode current VO< −0.5 V or >VCC+ 0.5V ±20 mA output source or sink
current
VO = −0.5 V to VCC+ 0.5V - ±35 mA
ICC, IGND VCC or GND current - ±70 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation
DIP20 package [1]- 750 mW
SO20 package [2]- 500 mW
Table 6: Recommended operating conditions
VCC supply voltage 2.0 5.0 6.0 V input voltage 0 - VCC V output voltage 0 - VCC V
tr, tf input rise and fall times VCC = 2.0 V - - 1000 ns
VCC = 4.5 V - 6.0 500 ns
VCC = 6.0 V - - 400 ns
Tamb ambient temperature −40 - +125 °C
Philips Semiconductors 74HC564
10. Static characteristics
Table 7: Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb =25°C
VIH HIGH-level input voltage VCC= 2.0V 1.5 1.2 - V
VCC= 4.5V 3.15 2.4 - V
VCC= 6.0V 4.2 3.2 - V
VIL LOW-level input voltage VCC= 2.0V - 0.8 0.5 V
VCC= 4.5V - 2.1 1.35 V
VCC= 6.0V - 2.8 1.8 V
VOH HIGH-level output voltage VI =VIHorVIL= −20 μA; VCC= 2.0V 1.9 2.0 - V= −20 μA; VCC= 4.5V 4.4 4.5 - V= −20 μA; VCC= 6.0V 5.9 6.0 - V= −6.0 mA; VCC= 4.5V 3.98 4.32- V= −7.8 mA; VCC= 6.0V 5.48 5.81- V
VOL LOW-level output voltage VI =VIHorVIL =20 μA; VCC= 2.0V - 0 0.1 V =20 μA; VCC= 4.5V - 0 0.1 V =20 μA; VCC= 6.0V - 0 0.1 V= 6.0 mA; VCC= 4.5V - 0.15 0.26 V= 7.8 mA; VCC= 6.0V - 0.16 0.26 V
ILI input leakage current VI =VCCor GND; VCC= 6.0V - - ±0.1 μA
IOZ 3-state OFF-state current VI =VIHor VIL; VCC= 6.0 V; VO =VCCor GND - - ±0.5 μA
ICC quiescent supply current VI =VCCor GND; IO=0 A; VCC= 6.0V - - 8.0 μA input capacitance - 3.5 - pF
Tamb= −40 °C to +85°C
VIH HIGH-level input voltage VCC= 2.0V 1.5 - - V
VCC= 4.5V 3.15- - V
VCC= 6.0V 4.2 - - V
VIL LOW-level input voltage VCC= 2.0V - - 0.5 V
VCC= 4.5V - - 1.35 V
VCC= 6.0V - - 1.8 V
VOH HIGH-level output voltage VI =VIHorVIL= −20 μA; VCC= 2.0V 1.9 - - V= −20 μA; VCC= 4.5V 4.4 - - V= −20 μA; VCC= 6.0V 5.9 - - V= −6.0 mA; VCC= 4.5V 3.84- - V= −7.8 mA; VCC= 6.0V 5.34- - V
Philips Semiconductors 74HC564
VOL LOW-level output voltage VI =VIHorVIL =20 μA; VCC= 2.0V - - 0.1 V =20 μA; VCC= 4.5V - - 0.1 V =20 μA; VCC= 6.0V - - 0.1 V= 6.0 mA; VCC= 4.5V - - 0.33 V= 7.8 mA; VCC= 6.0V - - 0.33 V
ILI input leakage current VI =VCCor GND; VCC= 6.0V - - ±1.0 μA
IOZ 3-state OFF-state current VI =VIHor VIL; VCC= 6.0 V; VO =VCCor GND - - ±5.0 μA
ICC quiescent supply current VI =VCCor GND; IO=0 A; VCC= 6.0V - - 80 μA
Tamb= −40 °C to +125°C
VIH HIGH-level input voltage VCC= 2.0V 1.5 - - V
VCC= 4.5V 3.15- - V
VCC= 6.0V 4.2 - - V
VIL LOW-level input voltage VCC= 2.0V - - 0.5 V
VCC= 4.5V - - 1.35 V
VCC= 6.0V - - 1.8 V
VOH HIGH-level output voltage VI =VIHorVIL -= −20 μA; VCC= 2.0V 1.9 - - V= −20 μA; VCC= 4.5V 4.4 - - V= −20 μA; VCC= 6.0V 5.9 - - V= −6.0 mA; VCC= 4.5V 3.7 - - V= −7.8 mA; VCC= 6.0V 5.2 - - V
VOL LOW-level output voltage VI =VIHorVIL - =20 μA; VCC= 2.0V - - 0.1 V =20 μA; VCC= 4.5V - - 0.1 V =20 μA; VCC= 6.0V - - 0.1 V= 6.0 mA; VCC= 4.5V - - 0.4 V= 7.8 mA; VCC= 6.0V - - 0.4 V
ILI input leakage current VI =VCCor GND; VCC= 6.0V - - ±1.0 μA
IOZ 3-state OFF-state current VI =VIHor VIL; VCC= 6.0 V; VO =VCCor GND - - ±10.0 μA
ICC quiescent supply current VI =VCCor GND; IO=0 A; VCC= 6.0V - - 160 μA
Table 7: Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Philips Semiconductors 74HC564
11. Dynamic characteristics
Table 8: Dynamic characteristics
GND= 0 V; tr=tf= 6 ns; CL= 50 pF; see Figure9.
Tamb = 25°C
tPHL, tPLH propagation delay CP toQn see Figure6
VCC = 2.0 V - 50 165 ns
VCC = 4.5 V - 18 33 ns
VCC = 6.0 V - 14 28 ns
VCC= 5.0 V; CL =15pF - 15 - ns
tPZH, tPZL 3-state output enable time OE to Qn see Figure7
VCC = 2.0 V - 44 140 ns
VCC = 4.5 V - 16 28 ns
VCC = 6.0 V - 13 24 ns
tPHZ, tPLZ 3-state output disable time OE toQn see Figure7
VCC = 2.0 V - 50 135 ns
VCC = 4.5 V - 18 27 ns
VCC = 6.0 V - 14 23 ns
tTHL, tTLH output transition time see Figure6
VCC = 2.0 V - 14 60 ns
VCC = 4.5 V - 5 12 ns
VCC = 6.0 V - 4 10 ns CP clock pulse width HIGH or LOW see Figure6
VCC = 2.0 V 80 14 - ns
VCC = 4.5 V 16 5 - ns
VCC = 6.0 V 14 4 - ns
tsu set-up time Dn to CP see Figure8
VCC = 2.0 V 60 6 - ns
VCC = 4.5 V 12 2 - ns
VCC = 6.0 V 10 2 - ns hold time Dn to CP see Figure8
VCC = 2.0 V 5 0 - ns
VCC = 4.5 V 5 0 - ns
VCC = 6.0 V 5 0 - ns
fmax maximum clock frequency see Figure6
VCC = 2.0 V 6.0 38 - MHz
VCC = 4.5 V 30 115 - MHz
VCC = 6.0 V 35 137 - MHz
VCC= 5.0 V; CL=15pF - 127 - MHz
CPD power dissipation capacitance per ﬂip-ﬂop VI= GND to VCC [1] -27 - pF

Partno	Mfg	Dc	Qty	Available	Descript
74HC564N	NXP	N/a	8	avai	Octal D-type flip-flop; positive-edge trigger; 3-state; inverting