74HC4094PW-74HCT4094D Fast Delivery |IC PHOENIX CO.,LIMITED

74HC4094PW ,74HC/HCT4094; 8-stage shift-and-store bus registerLogic diagram STAGE 0 STAGES 1 TO 6 STAGE 7D D Q D Q D Q QS1CP CPD Q QS2FF 0 FF 7CPCP LELATCHD Q D ..
74HC4094PW ,74HC/HCT4094; 8-stage shift-and-store bus registerApplications Serial-to-parallel data conversion Remote control holding register74HC4094; 74HCT409 ..
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74HC4094PW-74HCT4094D
8-stage shift-and-store bus register
1. General description
The 74HC4094; 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a
storage register and 3-state outputs. Both the shift and storage register have separate
clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to
enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is
available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when
clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW
transition of the CP input to allow cascading when clock edges are slow. The data in the
shift register is transferred to the storage register when the STR input is HIGH. Data in the
storage register appears at the outputs whenever the output enable input (OE) is HIGH. A
LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the
OE input does not affect the state of the registers. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits Complies with JEDEC standard JESD7A Input levels: For 74HC4094: CMOS level For 74HCT4094: TTL level Low-power dissipation ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Specified from 40 Cto+85 C and from 40 Cto+125C
3. Applications Serial-to-parallel data conversion Remote control holding register
74HC4094; 74HCT4094
8-stage shift-and-store bus register
Rev. 6 — 31 December 2012 Product data sheet
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
4. Ordering information
5. Functional diagram
Table 1. Ordering information
74HC4094N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT4094N
74HC4094D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width
3.9 mm
SOT109-1
74HCT4094D
74HC4094DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HCT4094DB
74HC4094PW 40 C to +125C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin description
STR 1 strobe input 2 data input 3 clock input
QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output
VSS 8 ground supply voltage
QS1, QS2 9, 10 serial output 15 output enable input
VDD 16 supply voltage
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
7. Functional description
[1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
 = positive-going transition;  = negative-going transition;
Z = HIGH-impedance OFF-state; NC = no change;
Q6S = the data in register stage 6 before the LOW to HIGH clock transition;
Q7S = the data in register stage 7 before the HIGH to LOW clock transition.
Table 3. Function table[1] L XXZ Z Q6S NC L XXZ Z NC Q7S HL X NC NC Q6S NC HH L L QPn 1Q6S NC H HHH QPn 1Q6S NC H H H NC NCNCQ7S
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
8. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70C.
[2] For SO16: Ptot derates linearly with 8 mW/K above 70C.
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60C.
9. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V - 20 mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V - 20 mA output current VO = 0.5 V to (VCC +0.5V) - 25 mA
ICC supply current - +50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation DIP16 package [1]- 750 mW
SO16, SSOP16 and TSSOP16 packages [2]- 500 mW
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V --83 - --ns/V
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
10. Static characteristicsTable 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC4094
VIH HIGH-level
input voltage
VCC= 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC= 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC= 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC= 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC= 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC= 6.0V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage =VIHorVIL= 20 A; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= 20 A; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= 20 A; VCC= 6.0V 5.9 6.0 - 5.9 - 5.9 - V= 4.0 mA; VCC= 4.5V 3.98 4.32 - 3.84 - 3.7 - V= 5.2 mA; VCC= 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage =VIHorVIL =20 A; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V =20 A; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V =20 A; VCC= 6.0V - 0 0.1 - 0.1 - 0.1 V= 4.0 mA; VCC= 4.5V - 0.15 0.26 - 0.33 - 0.4 V= 5.2 mA; VCC= 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =6.0V 0.1 - 1.0 - 1.0 A
IOZ OFF-state
output current =VIHor VIL; =VCCor GND;
VCC =6.0V 0.5 - 5.0 - 10.0 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =6.0V - 8.0 - 80 - 160 A input
capacitance
-3.5 - pF
74HCT4094
VIH HIGH-level
input voltage
VCC= 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC= 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage =VIHor VIL; VCC =4.5V= 20A 4.4 4.5 - 4.4 - 4.4 - V= 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage =VIHor VIL; VCC =4.5V =20A - 0 0.1 - 0.1 - 0.1 V= 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register input leakage
current =VCCor GND;
VCC =5.5V 0.1 - 1.0 - 1.0 A
IOZ OFF-state
output current =VIHor VIL; VCC =5.5V; =VCC or GND per input
pin; other inputs at VCC or
GND; IO =0A 0.5 - 5.0 - 10 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =5.5V - 8.0 - 80 - 160 A
ICC additional
supply current =VCC 2.1V;
other inputs at VCCor GND;
VCC= 4.5Vto 5.5V; =0A
per input pin; STR input - 100 360 - 450 - 490 A
per input pin; OE input - 150 540 - 675 - 735 A
per input pin; CP input - 150 540 - 675 - 735 A
per input pin; D input - 40 144 - 180 - 196 A input
capacitance
-3.5 - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
11. Dynamic characteristicsTable 7. Dynamic characteristics
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
74HC4094
tpd propagation
delay
CP to QS1; see Figure8 [1]
VCC = 2.0 V - 50 150 - 190 - 225 ns
VCC = 4.5 V - 18 30 - 38 - 45 ns
VCC =5V; CL =15pF - 15 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 38 ns
CP to QS2; see Figure8 [1]
VCC = 2.0 V - 44 135 - 170 - 205 ns
VCC = 4.5 V - 16 27 - 34 - 41 ns
VCC =5V; CL =15pF - 13 - - - - - ns
VCC = 6.0 V - 13 23 - 29 - 35 ns
CP to QPn; see Figure8 [1]
VCC = 2.0 V - 63 195 - 245 - 295 ns
VCC = 4.5 V - 23 39 - 49 - 59 ns
VCC =5V; CL =15pF - 20 - - - - - ns
VCC = 6.0 V - 18 33 - 42 - 50 ns
STR to QPn; see Figure9 [1]
VCC = 2.0 V - 58 180 - 225 - 270 ns
VCC = 4.5 V - 21 36 - 45 - 54 ns
VCC =5V; CL =15pF - 18 - - - - - ns
VCC = 6.0 V - 17 31 - 38 - 46 ns
ten enable time OE to QPn; see Figure11 [2]
VCC = 2.0 V - 55 175 - 220 - 265 ns
VCC = 4.5 V - 20 35 - 44 - 53 ns
VCC = 6.0 V - 16 30 - 37 - 45 ns
tdis disable time OE to QPn; see Figure11 [3]
VCC = 2.0 V - 41 125 - 155 - 190 ns
VCC = 4.5 V - 15 25 - 31 - 38 ns
VCC = 6.0 V - 12 21 - 26 - 32 ns transition
time
QPn and QSn; see
Figure8
[4]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register pulse width CP HIGH or LOW;
see Figure8
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
STR HIGH; see Figure9
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
tsu set-up time D to CP; see Figure10
VCC = 2.0 V 50 14 - 65 - 75 - ns
VCC = 4.5 V 10 5 - 13 - 15 - ns
VCC = 6.0 V 9 4 - 11 - 13 - ns
CP to STR; see Figure9
VCC = 2.0 V 100 28 - 125 - 150 - ns
VCC = 4.5 V 20 10 - 25 - 30 - ns
VCC = 6.0 V 17 8 - 21 - 26 - ns hold time D to CP; see Figure10
VCC = 2.0 V 3 -6 - 3 - 3 - ns
VCC = 4.5 V 3 -2 - 3 - 3 - ns
VCC = 6.0 V 3 -2 - 3 - 3 - ns
CP to STR; see Figure9
VCC = 2.0 V 0 -14 - 0 - 0 - ns
VCC = 4.5 V 0 -5 - 0 - 0 - ns
VCC = 6.0 V 0 -4 - 0 - 0 - ns
fmax maximum
frequency
CP; see Figure8
VCC = 2.0 V 6.0 28 - 4.8 - 4.0 - MHz
VCC = 4.5 V 30 87 - 24 - 20 - MHz
VCC =5V; CL =15pF - 95 - - - - - MHz
VCC = 6.0 V 35 103 - 28 - 24 - MHz
CPD power
dissipation
capacitance=50 pF;f= 1 MHz; =GNDto VCC
[5] -83 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
[1] tpd is the same as tPLH and tPHL.
74HCT4094
tpd propagation
delay
CP to QS1; see Figure8 [1]
VCC = 4.5 V - 23 39 - 49 - 59 ns
VCC =5V; CL =15pF - 19 - - - - - ns
CP to QS2; see Figure8 [1]
VCC = 4.5 V - 21 36 - 45 - 54 ns
VCC =5V; CL =15pF - 18 - - - - - ns
CP to QPn; see Figure8 [1]
VCC = 4.5 V - 25 43 - 54 - 65 ns
VCC =5V; CL =15pF - 21 - - - - - ns
STR to QPn; see Figure9 [1]
VCC = 4.5 V - 22 39 - 49 - 59 ns
VCC =5V; CL =15pF - 19 - - - - - ns
ten enable time OE to QPn; see Figure11 [2]
VCC = 4.5 V - 20 35 - 44 - 53 ns
tdis disable time OE to QPn; see Figure11 [3]
VCC = 4.5 V - 21 35 - 44 - 53 ns transition
time
QPn and QSn; see
Figure8
[4]
VCC = 4.5 V - 7 15 - 19 - 22 ns pulse width CP HIGH or LOW;
see Figure8
VCC = 4.5 V 16 7 - 20 - 24 - ns
STR HIGH; see Figure9
VCC = 4.5 V 16 5 - 20 - 24 - ns
tsu set-up time Dn to CP; see Figure10
VCC = 4.5 V 10 4 - 13 - 15 - ns
CP to STR; see Figure9
VCC = 4.5 V 20 9 - 25 - 30 - ns hold time Dn to CP; see Figure10
VCC = 4.5 V 4 0 - 4 - 4 - ns
CP to STR; see Figure9
VCC = 4.5 V 0 4- 0 - 0 - ns
fmax maximum
frequency
CP; see Figure8
VCC = 4.5 V 30 80 - 24 - 20 - MHz
VCC =5V; CL =15pF - 86 - - - - - MHz
CPD power
dissipation
capacitance=50 pF;f= 1 MHz; =GNDto VCC
[5] -92 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
[2] ten is the same as tPZH and tPZL.
[3] tdis is the same as tPLZ and tPHZ.
[4] tt is the same as tTHL and tTLH.
[5] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC = supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
12. Waveforms

Partno	Mfg	Dc	Qty	Available	Descript
74HC4094PW	NXP ?	N/a	20350	avai	74HC/HCT4094; 8-stage shift-and-store bus register
74HC4094PW	NXP	N/a	45520	avai	74HC/HCT4094; 8-stage shift-and-store bus register
74HCT4094D	NXP ?	N/a	19285	avai	8-stage shift-and-store bus register