74HC4094 ,8-stage shift-and-store bus registerM54HC4094M74HC40948 BIT SIPO SHIFT LATCH REGISTER (3-STATE). HIGH SPEEDfMAX = 73 MHz (TYP.) AT VCC ..
74HC4094D ,8-stage shift-and-store bus registerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC4094DB ,8-stage shift-and-store bus registerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC4094N ,74HC/HCT4094; 8-stage shift-and-store bus registerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC4094PW ,74HC/HCT4094; 8-stage shift-and-store bus registerLogic diagram STAGE 0 STAGES 1 TO 6 STAGE 7D D Q D Q D Q QS1CP CPD Q QS2FF 0 FF 7CPCP LELATCHD Q D ..
74HC4094PW ,74HC/HCT4094; 8-stage shift-and-store bus registerApplications Serial-to-parallel data conversion Remote control holding register74HC4094; 74HCT409 ..
74LVTH574WMX ,Low Voltage Octal D-Type Flip-Flop with 3-STATE OutputsFeaturesThe LVT574 and LVTH574 are high-speed, low-power
74HC4094
8-stage shift-and-store bus register
M54H C4094
M74HC4094 BIT SIPO SHIFT LATCH REGISTER (3-STATE)
B1R(Plastic Package)
ORDER CODES:M54HC4094F1R M74HC4094M1R
M74HC4094B1R M74HC4094C1R
F1R(CeramicPackage)
M1R(MicroPackage)
C1R(Chip Carrier)
PIN CONNECTIONS (top view)= Internal
DESCRIPTION HIGH SPEED
fMAX=73 MHz (TYP.) AT VCC =5V. LOWPOWER DISSIPATION
ICC =4 μA (MAX.) ATTA =25°C. HIGH NOISE IMMUNITY
VNIH =VNIL =28% VCC (MIN.). OUTPUT DRIVE CAPABILITY LSTTL LOADS. SYMMETRICAL OUTPUT IMPEDANCE
|IOH|= IOL=4 mA (MIN.). BALANCEDPROPAGATION DELAYS
tPLH =tPHL. WIDE OPERATING VOLTAGE RANGE
VCC (OPR)=2V TO6V. PIN AND FUNCTION COMPATIBLE
WITH 4094B
The M54/74HC4094isa high speed CMOS8 BIT
SIPO SHIFT LATCH REGISTERfabricated with sili-
con gateC2 MOS technology. has the same high speed performanceof LSTTL
combined with true CMOS low power consumption.
This device consistsofan 8-bit shift register andan
8-bit latch with 3-state output buffer. Datais shifted
serially through the shift register on the positive
going transitionof the clock input signal. The output the last stage (Qs) can be usedto cascade sev-
eral devices.
Dataon theQs output istransferred toa secondout-
put (Qs’)on the following negative transitionof the
clock input signal. The dataof eachstageof the shift
registeris provided witha latch, which latches data the negative going transitionof the STROBE
input signal. When the STROBE inputis held high,
datapropagates through thelatchtoa3-state output
buffer.
This bufferis enabled when OUTPUT ENABLE
inputis takenhigh.All inputs are equipped with pro-
LOGIC DIAGRAM
LOGIC DIAGRAM
M54/M74HC4094
TRUTH TABLE OE ST SI PARALLEL OUTPUT SERIAL OUTPUT Qn Qs Qs’ H L L Qn-1 Q7 NC H H H Qn-1 Q7 NC L X NCNCQ7 NC XXZ Z Q7 NC X NC NC NC Qs XXZ Z NC Qs Don’tCareZ: HighImpedance NC: NoChange
PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION STROBE Strobe Input SERIALIN Serial Input CLOCK Clock Input5,6,7,
14,13, 12,toQ7 Parallel Outputs10 QS Q’S Serial Outputs OE Output Enable Input GND Ground (0V) VCC Positive Supply Voltage
IEC LOGIC SYMBOL
INPUT AND OUTPUT EQUIVALENT CIRCUIT
M54/M74HC4094
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value UnitVCC Supply Voltage -0.5to+7 V DC Input Voltage -0.5to VCC+ 0.5 V DC Output Voltage -0.5to VCC+ 0.5 V
IIK DC Input Diode Current ±20 mA
IOK DC Output Diode Current ±20 mA DC Output Source Sink Current Per Output Pin ±25 mA
ICCor IGND DC VCCor Ground Current ±50 mA Power Dissipation 500(*) mW
Tstg Storage Temperature -65to +150 oC Lead Temperature (10 sec) 300 oC
Absolute MaximumRatings arethose values beyond whichdamage tothedevicemayoccur.Functional operation under theseconditionisnotimplied.
(*)500 mW:≅65oC derate to300mWby 10mW/oC:65o Cto85oC
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value UnitVCC Supply Voltage 2to6 V Input Voltage 0to VCC V Output Voltage 0to VCC V
Top Operating Temperature:
M54HC Series
M74HC Series
-55to +125
-40to +85CC
tr,tf Input Rise and Fall Time VCC=2V 0to 1000 ns
VCC=4.5V 0to 500
VCC=6V 0to 400
M54/M74HC4094
SPECIFICATIONSSymbol Parameter
Test Conditions Value
UnitVCC(V)
=25oC
54HC and 74HC
-40to85oC
74HC
-55to 125oC
54HC
Min. Typ. Max. Min. Max. Min. Max.VIH High Level Input
Voltage
2.0 1.5 1.5 1.54.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
VIL Low Level Input
Voltage
2.0 0.5 0.5 0.54.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
VOH High Level
Output Voltage
2.0 VI=
VIH
VIL
IO=-20μA
1.9 2.0 1.9 1.94.5 4.4 4.5 4.4 4.4
6.0 5.9 6.0 5.9 5.9
4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10
6.0 IO=-5.2 mA 5.68 5.8 5.63 5.60
VOL Low Level Output
Voltage
2.0 VI=
VIH
VIL
IO=20μA
0.0 0.1 0.1 0.14.5 0.0 0.1 0.1 0.1
6.0 0.0 0.1 0.1 0.1
4.5 IO= 4.0 mA 0.17 0.26 0.37 0.40
6.0 IO= 5.2 mA 0.18 0.26 0.37 0.40 Input Leakage
Current 6.0 VI =VCCor GND ±0.1 ±1 ±1 μA
IOZ 3 State Output
Off State Current
6.0 VI =VIHorVIL =VCCor GND
±0.5 ±5.0 ±10 μA
ICC Quiescent Supply
Current
6.0 VI =VCCor GND 4 40 80 μA
M54/M74HC4094
ELECTRICAL CHARACTERISTICS (CL =50 pF, Inputtr =tf =6 ns)
Symbol Parameter
Test Conditions Value
UnitVCC(V)
=25oC
54HC and 74HC
-40to85oC
74HC
-55to 125oC
54HC
Min. Typ. Max. Min. Max. Min. Max.tTLH
tTHL
Output Transition
Time
2.0 30 75 95 1104.5 8 151922
6.0 7 131619
tPLH
tPHL
Propagation
Delay Time
(CLOCK- Qn)
2.0 92 200 250 3004.5 26 40 50 60
6.0 20 34 43 51
tPLH
tPHL
Propagation
Delay Time LOCK -QS,Q’S)
2.0 65 150 190 2254.5 19 30 38 45
6.0 15 26 32 38
tPLH
tPHL
Propagation
Delay Time
(STROBE- Qn)
2.0 75 160 200 2404.5 20 32 40 48
6.0 16 27 34 41
tPZL
tPZH State Output
Enable Time
2.0 58 150 190 2254.5 16 30 38 45
6.0 13 26 32 38
tPHZ
tPLZ State Output
Disable Time
2.0 35 150 190 2254.5 16 30 38 45
6.0 13 26 32 38
fMAX Maximum Clock
Frequency
2.0 6 16 4.8 4
MHz4.5 30 66 24 20
6.0 35 80 28 24
tW(H)
tW(L)
Minimum Pulse
Width
2.0 17 75 95 1104.5 7 151922
6.0 6 131619
tW(L) Minimum Pulse
Width
2.0 28 75 95 1104.5 6 151922
6.0 6 131619 Minimum Set-up
Time
(SI)
2.0 30 75 95 1104.5 7 151922
6.0 5 131619 Minimum Set-up
Time
(ST)
2.0 45 100 125 1454.5 10 20 25 29
6.0 8 172125 Minimum Hold
Time
(SI, ST)
2.0 0 0 04.5 0 0 0
6.0 0 0 0
CIN Input Capacitance 5 10 10 10 pF
CPD(*) Power Dissipation
Capacitance
140 pF
(*) CPD isdefinedasthe valueofthe IC’sinternal equivalent capacitance which iscalculated fromthe operatingcurrent consumption without load.
(Referto Test Circuit).Average operting currentcanbe obtained bythefollowingequation. ICC(opr)=CPD •VCC •fIN+ICC/2(per FLIP/FLOP)
M54/M74HC4094
