74HC4067BQ-74HC4067DB-74HC4067PW-74HCT4067D-74HCT4067DB-74HCT4067N Fast Delivery |IC PHOENIX CO.,LIMITED

74HCT4067DB ,74HC/HCT4067; 16-channel analog multiplexer/demultiplexer 74HC4067; 74HCT406716-channel analog multiplexer/demultiplexerRev. 5 — 13 December 2011 Product da ..
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74HCT4075PW ,74HC/HCT4075; Triple 3-input OR gateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
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74VHCT74AM ,Dual D-Type Flip-Flop with Preset and ClearFeaturesThe VHCT74A is an advanced high speed CMOS Dual

74HC4067BQ-74HC4067DB-74HC4067PW-74HCT4067D-74HCT4067DB-74HCT4067N
16-channel analog multiplexer/demultiplexer
1. General description
The 74HC4067; 74HCT4067 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4067B. The device is specified in compliance with JEDEC standard no. 7A.
The 74HC4067; 74HCT4067 is a 16-channel analog multiplexer/demultiplexer with four
address inputs (S0 to S3), an active-LOW enable input (E), sixteen independent
inputs/outputs (Y0 to Y15) and a common input/output (Z).
The 74HC4067; 74HCT4067 contains sixteen bidirectional analog switches, each with
one side connected to an independent input/output (Y0 to Y15) and the other side
connected to a common input/output (Z).
With pin E = LOW, one of the sixteen switches is selected by pins S0 to S3 (low
impedance ON-state). All unselected switches are in the high-impedance OFF-state.
With pin E = HIGH, all switches are in the high-impedance OFF-state, independent of pins
S0 to S3.
The analog inputs/outputs (Y0 to Y15, and Z) can swing between VCC as a positive limit
and GND as a negative limit. VCC to GND may not exceed 10V.
2. Features and benefits Low ON resistance:80  (typical) at VCC = 4.5V70  (typical) at VCC = 6.0V60  (typical) at VCC = 9.0V Typical ‘break before make’ built-in
3. Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating
74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
Rev. 5 — 13 December 2011 Product data sheet
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
4. Ordering informationTable 1. Ordering information
74HC4067
74HC4067N 40 C to +125C DIP24 plastic dual in-line package; 24 leads (600 mil);
reverse bending
SOT101-1
74HC4067D 40 C to +125C SO24 plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
74HC4067DB 40 C to +125C SSOP24 plastic shrink small outline package; 24 leads;
body width 5.3 mm
SOT340-1
74HC4067PW 40 C to +125C TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
74HC4067BQ 40 C to +125C DHVQFN24 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 24 terminals;
body 3.5 5.5 0.85 mm
SOT815-1
74HCT4067
74HCT4067N 40 C to +125C DIP24 plastic dual in-line package; 24 leads (600 mil);
reverse bending
SOT101-1
74HCT4067D 40 C to +125C SO24 plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
74HCT4067DB 40 C to +125C SSOP24 plastic shrink small outline package; 24 leads;
body width 5.3 mm
SOT340-1
74HCT4067PW 40 C to +125C TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
74HCT4067BQ 40 C to +125C DHVQFN24 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 24 terminals;
body 3.5 5.5 0.85 mm
SOT815-1
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
5. Functional diagram
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin description 1 common input or output
Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0, Y15,
Y14, Y13, Y12, Y11, Y10, Y9, Y8
2, 3, 4, 5, 6, 7, 8, 9, 16, 17, 18, 19, 20, 21, 22, 23 independent input or output
S0, S1, S3, S2 10, 11, 13, 14 address input 0
GND 12 ground (0V) 15 enable input (active LOW)
VCC 24 supply voltage
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
7. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
8. Limiting values
Table 3. Function table[1] LLL LY0 to Z LLL H Y1 to Z LLH LY2 to Z LLH H Y3 to Z L H L L Y4 to Z L HL HY5 to Z L H H L Y6 to Z L HH HY7 to Z H LL LY8 to Z H L L H Y9 to Z H LH LY10 to Z H L H H Y11 to Z HHL L Y12 to Z HHL HY13 to Z HHH L Y14 to Z HHH HY15 to Z XXX X-
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage [1] 0.5 +11.0 V
IIK input clamping current VI< 0.5 V or VI >VCC +0.5V - 20 mA
ISK switch clamping current VSW< 0.5 V or VSW >VCC +0.5V - 20 mA
ISW switch current VSW= 0.5 V to VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
[1] To avoid drawing VCC current out of terminal Z, when switch current flows in terminals Yn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VCC current will flow out of terminals Yn. In this case there is
no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed VCC or GND.
[2] For DIP24 package: Ptot derates linearly with 12 mW/K above 70C.
[3] For SO24 package: Ptot derates linearly with 8 mW/K above 70C.
[4] For SSOP24 and TSSOP24 packages: Ptot derates linearly with 5.5 mW/K above 60C.
[5] For DHVQFN24 package: Ptot derates linearly with 4.5 mW/K above 60C.
9. Recommended operating conditions
Ptot total power dissipation Tamb = 40 C to +125C
DIP24 package [2] -750 mW
SO24 package [3] -500 mW
SSOP24 package [4] -500 mW
TSSOP24 package [4] -500 mW
DHVQFN24 package [5] -500 mW power dissipation per switch - 100 mW
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
Table 5. Recommended operating conditions
74HC4067
VCC supply voltage 2.0 5.0 10.0 V input voltage GND - VCC V
VSW switch voltage GND - VCC V
t/V input transition rise and fall rate VCC= 2.0V - - 625 ns
VCC= 4.5V - 1.67 139 ns
VCC =6.0V - - 83 ns
VCC= 10.0V - - 31 ns
Tamb ambient temperature 40 +25 +125 C
74HCT4067
VCC supply voltage 4.5 5.0 5.5 V input voltage GND - VCC V
VSW switch voltage GND - VCC V
t/V input transition rise and fall rate VCC = 4.5V - 1.67 139 ns
Tamb ambient temperature 40 +25 +125 C
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
10. Static characteristics
[1] At supply voltages (VCC  GND) approaching 2 V, the analog switch ON resistance becomes extremely non-linear. Therefore it is
recommended that these devices be used to transmit digital signals only, when using these supply voltages.
Table 6. RON resistance per switch for types 74HC4067 and 74HCT4067
VI = VIH or VIL; for test circuit see Figure8.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
For 74HC4067: VCC  GND = 2.0 V, 4.5 V, 6.0 V and 9.0V.
For 74HCT4067: VCC  GND = 4.5V.
RON(peak) ON resistance (peak) Vis = VCC to GND
VCC = 2.0 V; ISW = 100A [1] - --- 
VCC = 4.5 V; ISW = 1000A 110 180 225 270 
VCC = 6.0 V; ISW = 1000A 95 160 200 240 
VCC = 9.0 V; ISW = 1000A 75 130 165 195 
RON(rail) ON resistance (rail) Vis = GND or VCC
VCC = 2.0 V; ISW = 100A [1] 150 ---
VCC = 4.5 V; ISW = 1000A 90 160 200 240 
VCC = 6.0 V; ISW = 1000A 80 140 175 210 
VCC = 9.0 V; ISW = 1000A 70 120 150 180 
RON ON resistance mismatch
between channels
Vis = VCC to GND
VCC = 2.0V [1] - --- 
VCC = 4.5V 9 --- 
VCC = 6.0V 8 --- 
VCC = 9.0V 6 --- 
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
Table 7. Static characteristics 74HC4067
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Tamb = 25C
VIH HIGH-level input voltage VCC = 2.0V 1.5 1.2 - V
VCC = 4.5V 3.15 2.4 - V
VCC = 6.0V 4.2 3.2 - V
VCC = 9.0V 6.3 4.7 - V
VIL LOW-level input voltage VCC = 2.0V - 0.8 0.5 V
VCC = 4.5V - 2.1 1.35 V
VCC = 6.0V - 2.8 1.80 V
VCC = 9.0V - 4.3 2.70 V input leakage current VI = VCC or GND
VCC = 6.0V - - 0.1 A
VCC = 10.0V - - 0.2 A
IS(OFF) OFF-state leakage current VCC = 10.0 V; VI = VIH or VIL; VSW= VCC GND; see Figure10
per channel - - 0.1 A
all channels - - 0.8 A
IS(ON) ON-state leakage current VCC = 10.0 V; VI = VIH or VIL; VSW= VCC GND; see Figure11 0.8 A
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =VCC or GND
VCC = 6.0V - - 8.0 A
VCC = 10.0V - - 16.0 A input capacitance - 3.5 - pF
Tamb = 40 C to +85C
VIH HIGH-level input voltage VCC = 2.0V 1.5 - - V
VCC = 4.5V 3.15 - - V
VCC = 6.0V 4.2 - - V
VCC = 9.0V 6.3 - - V
VIL LOW-level input voltage VCC = 2.0V - - 0.50 V
VCC = 4.5V - - 1.35 V
VCC = 6.0V - - 1.80 V
VCC = 9.0V - - 2.70 V input leakage current VI = VCC or GND
VCC = 6.0V - - 1.0 A
VCC = 10.0V - - 2.0 A
IS(OFF) OFF-state leakage current VCC = 10.0 V; VI = VIH or VIL; VSW= VCC GND; see Figure10
per channel - - 1.0 A
all channels - - 8.0 A
IS(ON) ON-state leakage current VCC = 10.0 V; VI = VIH or VIL; VSW= VCC GND; see Figure11 8.0 A
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =VCC or GND
VCC = 6.0V - - 80.0 A
VCC = 10.0V - - 160 A
Tamb = 40 C to +125C
VIH HIGH-level input voltage VCC = 2.0V 1.5 - - V
VCC = 4.5V 3.15 - - V
VCC = 6.0V 4.2 - - V
VCC = 9.0V 6.3 - - V
VIL LOW-level input voltage VCC = 2.0V - - 0.50 V
VCC = 4.5V - - 1.35 V
VCC = 6.0V - - 1.80 V
VCC = 9.0V - - 2.70 V input leakage current VI = VCC or GND
VCC = 6.0V - - 1.0 A
VCC = 10.0V - - 2.0 A
Table 7. Static characteristics 74HC4067 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
IS(OFF) OFF-state leakage current VCC = 10.0 V; VI = VIH or VIL; VSW= VCC GND; see Figure10
per channel - - 1.0 A
all channels - - 8.0 A
IS(ON) ON-state leakage current VCC = 10.0 V; VI = VIH or VIL; VSW= VCC GND; see Figure11 8.0 A
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =VCC or GND
VCC = 6.0V - - 160 A
VCC = 10.0V - - 320 A
Table 7. Static characteristics 74HC4067 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Table 8. Static characteristics 74HCT4067
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Tamb = 25C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5V 2.0 1.6 - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5V - 1.2 0.8 V input leakage current VI = VCC or GND; VCC = 5.5V - - 0.1 A
IS(OFF) OFF-state leakage current VCC = 5.5 V; VI = VIH or VIL; VSW= VCC GND; see Figure10
per channel - - 0.1 A
all channels - - 0.8 A
IS(ON) ON-state leakage current VCC = 5.5 V; VI = VIH or VIL; VSW= VCC GND; see Figure11 0.8 A
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =VCC or GND; VCC = 4.5 V to 5.5V
--8.0 A
ICC additional supply current per input pin; VI = VCC  2.1 V; other inputs
at VCC or GND; VCC = 4.5 V to 5.5V
pin E - 60 216 A
pin Sn - 50 180 A input capacitance - 3.5 - pF
Tamb = 40 C to +85C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5V - - 0.8 V input leakage current VI = VCC or GND; VCC = 5.5V - - 1.0 A
IS(OFF) OFF-state leakage current VCC = 5.5 V; VI = VIH or VIL; VSW= VCC GND; see Figure10
per channel - - 1.0 A
all channels - - 8.0 A
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
IS(ON) ON-state leakage current VCC = 5.5 V; VI = VIH or VIL; VSW= VCC GND; see Figure11 8.0 A
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =VCC or GND; VCC = 4.5 V to 5.5V - 80.0 A
ICC additional supply current per input pin; VI = VCC  2.1 V; other inputs
at VCC or GND; VCC = 4.5 V to 5.5V
pin E - - 270 A
pin Sn - - 225 A
Tamb = 40 C to +125C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5V - - 0.8 V input leakage current VI = VCC or GND; VCC = 5.5V - - 1.0 A
IS(OFF) OFF-state leakage current VCC = 5.5 V; VI = VIH or VIL; VSW= VCC GND; see Figure10
per channel - - 1.0 A
all channels - - 8.0 A
IS(ON) ON-state leakage current VCC = 5.5 V; VI = VIH or VIL; VSW= VCC GND; see Figure11 8.0 A
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =VCC or GND; VCC = 4.5 V to 5.5V - 160 A
ICC additional supply current per input pin; VI = VCC  2.1 V; other inputs
at VCC or GND; VCC = 4.5 V to 5.5V
pin E - - 294 A
pin Sn - - 245 A
Table 8. Static characteristics 74HCT4067 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
11. Dynamic characteristicsTable 9. Dynamic characteristics 74HC4067
GND =0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 14.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
tpd propagation delay Yn to Z; see Figure12 [1][2]
VCC = 2.0V 25 75 95 110 ns
VCC = 4.5V 9 15 19 22 ns
VCC = 6.0V 7 13 16 19 ns
VCC = 9.0V 5 9 11 14 ns
Z to Yn
VCC = 2.0V 18 60 75 90 ns
VCC = 4.5V 6 12 15 18 ns
VCC = 6.0V 5 10 13 15 ns
VCC = 9.0V 4 8 10 12 ns
toff turn-off time E to Yn; see Figure13 [3]
VCC = 2.0V 74 250 315 375 ns
VCC = 4.5V 27 50 63 75 ns
VCC = 5.0 V; CL = 15pF 27 - - - ns
VCC = 6.0V 22 43 54 64 ns
VCC = 9.0V 20 38 48 57 ns
Sn to Yn
VCC = 2.0V 83 250 315 375 ns
VCC = 4.5V 30 50 63 75 ns
VCC = 5.0 V; CL = 15pF 29 - - - ns
VCC = 6.0V 24 43 54 64 ns
VCC = 9.0V 21 38 48 57 ns
E to Z
VCC = 2.0V 85 275 345 415 ns
VCC = 4.5V 31 55 69 83 ns
VCC = 6.0V 25 47 59 71 ns
VCC = 9.0V 24 42 53 63 ns
Sn to Z
VCC = 2.0V 94 290 365 435 ns
VCC = 4.5V 34 58 73 87 ns
VCC = 6.0V 27 47 62 74 ns
VCC = 9.0V 25 45 56 68 ns
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
[1] tpd is the same as tPHL and tPLH.
[2] Due to higher Z terminal capacitance (16 switches versus 1) the delay figures to the Z terminal are higher than those to the Y terminal.
[3] ton is the same as tPHZ and tPLZ.
[4] toff is the same as tPZH and tPZL.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2fi+ {(CL +Csw)  VCC2  fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
{(CL +Csw)  VCC2  fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
ton turn-on time E to Yn; see Figure13 [4]
VCC = 2.0V 80 275 345 415 ns
VCC = 4.5V 29 55 69 83 ns
VCC = 5.0 V; CL = 15pF 26 - - - ns
VCC = 6.0V 23 47 59 71 ns
VCC = 9.0V 17 42 53 63 ns
Sn to Yn
VCC = 2.0V 88 300 375 450 ns
VCC = 4.5V 32 60 75 90 ns
VCC = 5.0 V; CL = 15pF 29 - - - ns
VCC = 6.0V 26 51 64 77 ns
VCC = 9.0V 18 45 56 68 ns
E to Z
VCC = 2.0V 85 275 345 415 ns
VCC = 4.5V 31 55 69 83 ns
VCC = 6.0V 25 47 59 71 ns
VCC = 9.0V 18 42 53 63 ns
Sn to Z
VCC = 2.0V 94 300 375 450 ns
VCC = 4.5V 34 60 75 90 ns
VCC = 6.0V 27 51 64 77 ns
VCC = 9.0V 19 45 56 68 ns
CPD power dissipation
capacitance
per switch; VI = GND to VCC [5] 29 - - - pF
Table 9. Dynamic characteristics 74HC4067 …continued
GND =0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 14.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.

Partno	Mfg	Dc	Qty	Available	Descript
74HC4067BQ	PHI	N/a	7940	avai	16-channel analog multiplexer/demultiplexer
74HC4067DB	NXP	N/a	1000	avai	16-channel analog multiplexer/demultiplexer
74HC4067PW	NXP	N/a	13368	avai	74HC/HCT4067; 16-channel analog multiplexer/demultiplexer
74HCT4067D	NXP	N/a	15560	avai	74HC/HCT4067; 16-channel analog multiplexer/demultiplexer
74HCT4067DB	NXP	N/a	45220	avai	74HC/HCT4067; 16-channel analog multiplexer/demultiplexer
74HCT4067N	NXP	N/a	50	avai	16-channel analog multiplexer/demultiplexer