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74HC4066DNXPN/a46654avaiQuad single-pole single-throw analog switch
74HCT4066BQNXP/PHILIPSN/a51000avaiQuad single-pole single-throw analog switch
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74HC4066D-74HCT4066BQ-74HCT4066PW
Quad single-pole single-throw analog switch
1. General description
The 74HC4066; 74HCT4066 is a quad single pole, single throw analog switch. Each
switch features two input/output terminals (nY and nZ) and an active HIGH enable input
(nE). When nE is LOW, the analog switch is turned off. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits
Input levels nE inputs: For 74HC4066: CMOS level For 74HCT4066: TTL level Low ON resistance:50  (typical) at VCC = 4.5V45  (typical) at VCC = 6.0V35  (typical) at VCC = 9.0V Specified in compliance with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Specified from 40 Cto +85 C and 40 Cto +125C
74HC4066; 74HCT4066
Quad single-pole single-throw analog switch
Rev. 7 — 2 April 2013 Product data sheet
NXP Semiconductors 74HC4066; 74HCT4066
Quad single-pole single-throw analog switch
3. Ordering information

4. Functional diagram

Table 1. Ordering information

74HC4066N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT4066N
74HC4066D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HCT4066D
74HC4066DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT337-1
74HCT4066DB
74HC4066PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
SOT402-1
74HCT4066PW
74HC4066BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.53 0.85 mm
SOT762-1
74HCT4066BQ
NXP Semiconductors 74HC4066; 74HCT4066
Quad single-pole single-throw analog switch

5. Pinning information
5.1 Pinning
5.2 Pin description

Table 2. Pin description

1Z, 2Z, 3Z, 4Z 2, 3, 9, 10 independent input or output , 2Y, 3Y, 4Y 1, 4, 8, 11 independent input or output
GND 7 ground (0V) 13, 5, 6, 12 enable input (active HIGH) 14 supply voltage
NXP Semiconductors 74HC4066; 74HCT4066
Quad single-pole single-throw analog switch
6. Functional description

[1] H = HIGH voltage level;
L = LOW voltage level.
7. Limiting values

[1] To avoid drawing VCC current out of terminal Z, when switch current flows in terminals Yn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VCC current will flow out of terminals Yn. In this case there is
no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed VCC or GND.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60C.
Table 3. Function table[1]

LOFF
HON
Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage 0.5 +11.0 V
IIK input clamping current VI< 0.5 V or VI >VCC +0.5V - 20 mA
ISK switch clamping current VSW< 0.5 V or VSW >VCC +0.5V - 20 mA
ISW switch current VSW= 0.5 V to VCC +0.5V [1]- 25 mA
ICC supply current - 50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125C [2]
DIP14 package - 750
SO14, (T)SSOP14 and DHVQFN14
packages
-500 power dissipation per switch - 100 mW
NXP Semiconductors 74HC4066; 74HCT4066
Quad single-pole single-throw analog switch
8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating conditions

VCC supply voltage 2.0 5.0 10.0 4.5 5.0 5.5 V input voltage GND - VCC GND - VCC V
VSW switch voltage GND - VCC GND - VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise
and fall rate
VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
VCC = 10.0 V - - 35 - - - ns/V
Table 6. RON resistance per switch for types 74HC4066 and 74HCT4066

VI = VIH or VIL; for test circuit see Figure6.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
For 74HC4066: VCC  GND = 2.0 V, 4.5 V, 6.0 V and 9.0V.
For 74HCT4066: VCC  GND = 4.5V.
RON(peak) ON resistance (peak) Vis = VCC to GND
VCC = 2.0 V; ISW = 100A [2] --- - - 
VCC = 4.5 V; ISW = 1000A - 54 - 118 142 
VCC = 6.0 V; ISW = 1000A - 42 - 105 126 
VCC = 9.0 V; ISW = 1000A - 32 - 88 105 
RON(rail) ON resistance (rail) Vis = GND
VCC = 2.0 V; ISW = 100A [2] -80- - - 
VCC = 4.5 V; ISW = 1000 A- 35 - 95 115 
VCC = 6.0 V; ISW = 1000A - 27 - 82 100 
VCC = 9.0 V; ISW = 1000 A- 20 - 70 85 
Vis = VCC
VCC = 2.0 V; ISW = 100A [2] -100 - - - 
VCC = 4.5 V; ISW = 1000A - 42 - 106 128 
VCC = 6.0 V; ISW = 1000 A- 35 - 94 113 
VCC = 9.0 V; ISW = 1000 A- 20 - 78 95 
NXP Semiconductors 74HC4066; 74HCT4066
Quad single-pole single-throw analog switch

[1] Typical values are measured at Tamb= 25 C.
[2] At supply voltages (VCC  GND) approaching 2 V, the analog switch ON resistance becomes extremely non-linear. Therefore it is
recommended that these devices be used to transmit digital signals only, when using these supply voltages.
RON ON resistance
mismatch between
channels
Vis = VCC to GND
VCC = 2.0V [2] --- - - 
VCC = 4.5V - 5 - - - 
VCC = 6.0V - 4 - - - 
VCC = 9.0V - 3 - - - 
Table 6. RON resistance per switch for types 74HC4066 and 74HCT4066 …continued

VI = VIH or VIL; for test circuit see Figure6.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
For 74HC4066: VCC  GND = 2.0 V, 4.5 V, 6.0 V and 9.0V.
For 74HCT4066: VCC  GND = 4.5V.
NXP Semiconductors 74HC4066; 74HCT4066
Quad single-pole single-throw analog switch
Table 7. Static characteristics 74HC4066
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Tamb = 40
C to +85C
VIH HIGH-level input voltage VCC = 2.0V 1.5 1.2 - V
VCC = 4.5V 3.15 2.4 - V
VCC = 6.0V 4.2 3.2 - V
VCC = 9.0V 6.3 4.7 - V
VIL LOW-level input voltage VCC = 2.0V - 0.8 0.5 V
VCC = 4.5V - 2.1 1.35 V
VCC = 6.0V - 2.8 1.80 V
VCC = 9.0V - 4.3 2.70 V input leakage current VI = VCC or GND
VCC = 6.0V - - 1.0 A
VCC = 10.0V - - 2.0 A
IS(OFF) OFF-state leakage current VCC = 10.0 V; VI = VIH or VIL; VSW =VCC GND; see Figure8
per channel - - 1.0 A
IS(ON) ON-state leakage current VCC = 10.0 V; VI = VIH or VIL; VSW =VCC GND; see Figure9 1.0 A
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =VCC or GND
VCC = 6.0V - - 20.0 A
VCC = 10.0V - - 40.0 A input capacitance - 3.5 - pF
Csw switch capacitance - 8 - pF
Tamb = 40
C to +125C
VIH HIGH-level input voltage VCC = 2.0V 1.5 - - V
VCC = 4.5V 3.15 - - V
VCC = 6.0V 4.2 - - V
VCC = 9.0V 6.3 - - V
VIL LOW-level input voltage VCC = 2.0V - - 0.50 V
VCC = 4.5V - - 1.35 V
VCC = 6.0V - - 1.80 V
VCC = 9.0V - - 2.70 V input leakage current VI = VCC or GND
VCC = 6.0V - - 1.0 A
VCC = 10.0V - - 2.0 A
IS(OFF) OFF-state leakage current VCC = 10.0 V; VI = VIH or VIL; VSW =VCC GND; see Figure8
per channel - - 1.0 A
IS(ON) ON-state leakage current VCC = 10.0 V; VI = VIH or VIL; VSW =VCC GND; see Figure9 1.0 A
NXP Semiconductors 74HC4066; 74HCT4066
Quad single-pole single-throw analog switch

[1] Typical values are measured at Tamb= 25 C.
[1] Typical values are measured at Tamb= 25 C.
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =VCC or GND
VCC = 6.0V - - 40 A
VCC = 10.0V - - 80 A
Table 7. Static characteristics 74HC4066 …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Table 8. Static characteristics 74HCT4066

At recommended operating conditions; voltages are referenced to GND (ground = 0V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Tamb = 40
C to +85C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5V 2.0 1.6 - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5V - 1.2 0.8 V input leakage current VI = VCC or GND; VCC = 5.5V - - 1.0 A
IS(OFF) OFF-state leakage current VCC = 5.5 V; VI = VIH or VIL; VSW =VCC GND; see Figure8
per channel - - 1.0 A
IS(ON) ON-state leakage current VCC = 5.5 V; VI = VIH or VIL; VSW =VCC GND; see Figure9 1.0 A
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =VCC or GND; VCC = 4.5 V to 5.5V - 20.0 A
ICC additional supply current per input pin; VI = VCC  2.1 V; other inputs
at VCC or GND; VCC = 4.5 V to 5.5V 100 450 A input capacitance - 3.5 - pF
Csw switch capacitance - 8 - pF
Tamb = 40
C to +125C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5V - - 0.8 V input leakage current VI = VCC or GND; VCC = 5.5V - - 1.0 A
IS(OFF) OFF-state leakage current VCC = 5.5 V; VI = VIH or VIL; VSW =VCC GND; see Figure8
per channel - - 1.0 A
IS(ON) ON-state leakage current VCC = 5.5 V; VI = VIH or VIL; VSW =VCC GND; see Figure9 1.0 A
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =VCC or GND; VCC = 4.5 V to 5.5V 40 A
ICC additional supply current per input pin; VI = VCC  2.1 V; other inputs
at VCC or GND; VCC = 4.5 V to 5.5V - 490 A
NXP Semiconductors 74HC4066; 74HCT4066
Quad single-pole single-throw analog switch

10. Dynamic characteristics

[1] Typical values are measured at Tamb= 25 C.
[2] tpd is the same as tPHL and tPLH.
[3] ton is the same as tPHZ and tPLZ.
Table 9. Dynamic characteristics 74HC4066

GND =0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 12.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
tpd propagation delay nYto nZ or nZto nY; RL =  ;
see Figure10
[2]
VCC = 2.0V - 8 75 - 90 ns
VCC = 4.5V - 3 15 - 18 ns
VCC = 6.0V - 2 13 - 15 ns
VCC = 9.0V - 2 10 - 12 ns
toff turn-off time nEto nY or nZ; see Figure11 [4]
VCC = 2.0 V - 44 190 - 225 ns
VCC = 4.5 V - 16 38 - 45 ns
VCC = 5.0 V; CL = 15pF - 13 - - - ns
VCC = 6.0 V - 13 33 - 38 ns
VCC = 9.0 V - 16 26 - 30 ns
ton turn-on time nEto nY or nZ; see Figure11 [3]
VCC = 2.0 V - 36 125 - 150 ns
VCC = 4.5 V - 13 25 - 30 ns
VCC = 5.0 V; CL = 15pF - 11 - - - ns
VCC = 6.0 V - 10 21 - 26 ns
VCC = 9.0 V - 8 16 - 20 ns
CPD power dissipation
capacitance
per switch; VI = GND to VCC [5] 11 - - - pF
NXP Semiconductors 74HC4066; 74HCT4066
Quad single-pole single-throw analog switch

[4] toff is the same as tPZH and tPZL.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2fi+ {(CL +Csw)  VCC2  fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
{(CL +Csw)  VCC2  fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
[1] Typical values are measured at Tamb= 25 C.
[2] tpd is the same as tPHL and tPLH.
[3] ton is the same as tPHZ and tPLZ.
[4] toff is the same as tPZH and tPZL.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2fi+ {(CL +Csw)  VCC2  fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
{(CL +Csw)  VCC2  fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
Table 10. Dynamic characteristics 74HCT4066

GND =0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 12.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
tpd propagation
delayto nZ or nZto nY; RL =  ;
see Figure10
[2]
VCC = 4.5V - 3 15 - 18 ns
toff turn-off time nEto nY or nZ; see Figure11 [4]
VCC = 4.5V - 20 44 - 53 ns
VCC = 5.0 V; CL = 15pF - 16 - - - ns
ton turn-on time nEto nY or nZ; see Figure11 [3]
VCC = 4.5V - 12 30 - 36 ns
VCC = 5.0 V; CL = 15pF - 12 - - - ns
CPD power dissipation
capacitance
per switch; =GNDto (VCC 1.5V)
[5] -12- - - pF
NXP Semiconductors 74HC4066; 74HCT4066
Quad single-pole single-throw analog switch
11. Waveforms

Table 11. Measurement points

74HC4066 VCC 0.5VCC
74HCT4066 3.0V 1.3V
NXP Semiconductors 74HC4066; 74HCT4066
Quad single-pole single-throw analog switch

[1] For 74HCT4066: maximum input voltage VI = 3.0V.
Table 12. Test data

tPHL, tPLH GND GND to VCC 6ns 50pF - open
tPHZ, tPZH GND to VCC VCC 6ns 50pF, 15pF 1k GND
tPLZ, tPZL GND to VCC GND 6ns 50 pF, 15pF 1k VCC
NXP Semiconductors 74HC4066; 74HCT4066
Quad single-pole single-throw analog switch
12. Additional dynamic characteristics

[1] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600).
[2] Adjust input voltage Vis to 0 dBm level at Vos for fi = 1 MHz (0 dBm = 1 mW into 50 ). After set-up, fi is increased to obtain a reading of
3dB at Vos.
Table 13. Additional dynamic characteristics

Recommended conditions and typical values; GND = 0 V; Tamb = 25 C.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
THD total harmonic distortion fi=1 kHz; RL = 10 k; CL =50pF;
see Figure13
VCC = 4.5 V; VI= 4.0 V (p-p) - 0.04 - %
VCC = 9.0 V; VI= 8.0 V (p-p) - 0.02 - % =10 kHz; RL = 10 k; CL =50pF;
see Figure13
VCC = 4.5 V; VI= 4.0 V (p-p) - 0.12 - %
VCC = 9.0 V; VI= 8.0 V (p-p) - 0.06 - %
f(3dB) 3 dB frequency response RL = 50 ; CL =10 pF; see Figure15 [2]
VCC = 4.5 V - 180 - MHz
VCC = 9.0 V - 200 - MHz
iso isolation (OFF-state) RL = 600 ; CL =50 pF; fi=1 MHz;
see Figure14
[1]
VCC = 4.5 V - 50 - dB
VCC = 9.0 V - 50 - dB
Vct crosstalk voltage between digital input and switch (peak to
peak value); RL= 600 ; CL =50pF; =1 MHz; see Figure16
VCC = 4.5 V - 110 - mV
VCC = 9.0 V - 220 - mV
Xtalk crosstalk between switches; RL= 600 ; CL =50pF; =1 MHz; see Figure17
[1]
VCC = 4.5 V - 60 - dB
VCC = 9.0 V - 60 - dB
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