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74HC4046ADB-74HC4046AN-74HCT4046ADB-74HCT4046AN
74HC/HCT4046A; Phase-locked-loop with VCO
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
FEATURES Low power consumption Centre frequency of up to 17 MHz (typ.) at VCC= 4.5V Choice of three phase comparators: EXCLUSIVE-OR;
edge-triggered JK flip-flop;
edge-triggered RS flip-flop Excellent VCO frequency linearity VCO-inhibit control for ON/OFF keying and for low
standby power consumption Minimal frequency drift Operating power supply voltage range:
VCO section 3.0 to 6.0V
digital section 2.0 to 6.0V Zero voltage offset due to op-amp buffering Output capability: standard ICC category: MSI.
GENERAL DESCRIPTIONThe 74HC/HCT4046A are high-speed Si-gate CMOS
devices and are pin compatible with the “4046” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4046A are phase-locked-loop circuits that
comprise a linear voltage-controlled oscillator (VCO) and
three different phase comparators (PC1, PC2 and PC3)
with a common signal input amplifier and a common
comparator input.
The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small
voltage signals within the linear region of the input
amplifiers. With a passive low-pass filter, the “4046A”
forms a second-order loop PLL. The excellent VCO
linearity is achieved by the use of linear op-amp
techniques.
The VCO requires one external capacitor C1 (between
C1A and C1B) and one external resistor R1 (between and GND) or two external resistors R1 and R2
(between R1 and GND, and R2 and GND). Resistor R1
and capacitor C1 determine the frequency range of the
VCO. Resistor R2 enables the VCO to have a frequency
offset if required.
The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is
provided at pin 10 (DEMOUT). In contrast to conventional
techniques where the DEMOUT voltage is one threshold
voltage lower than the VCO input voltage, here the
DEMOUT voltage equals that of the VCO input. If
DEMOUT is used, a load resistor (RS) should be connected
from DEMOUT to GND; if unused, DEMOUT should be left
open. The VCO output (VCOOUT) can be connected
directly to the comparator input (COMPIN), or connected
via a frequency-divider. The VCO output signal has a duty
factor of 50% (maximum expected deviation 1%), if the
VCO input is held at a constant DC level. A LOW level at
the inhibit input (INH) enables the VCO and demodulator,
while a HIGH level turns both off to minimize standby
power consumption.
The only difference between the HC and HCT versions is
the input level specification of the INH input. This input
disables the VCO section. The sections of the comparator
are identical, so that there is no difference in the
SIGIN (pin 14) or COMPIN (pin 3) inputs between the HC
and HCT versions.
Phase comparatorsThe signal input (SIGIN) can be directly coupled to the
self-biasing amplifier at pin 14, provided that the signal
swing is between the standard HC family input logic levels.
Capacitive coupling is required for signals with smaller
swings.
Phase comparator 1 (PC1)
This is an EXCLUSIVE-OR network. The signal and
comparator input frequencies (fi) must have a 50% duty
factor to obtain the maximum locking range. The transfer
characteristic of PC1, assuming ripple (fr =2fi) is
suppressed, is:
where VDEMOUT is the demodulator output at pin 10;
VDEMOUT =VPC1OUT (via low-pass filter).
The phase comparator gain is:
The average output voltage from PC1, fed to the VCO
input via the low-pass filter and seen at the demodulator
output at pin 10 (VDEMOUT), is the resultant of the phase
differences of signals (SIGIN) and the comparator input
(COMPIN) as shown in Fig.6. The average of VDEMOUTis
equal to1 ⁄2VCC when there is no signal or noise at
SIGIN and with this input the VCO oscillates at the centre
frequency (fo). Typical waveforms for the PC1 loop locked
at fo are shown in Fig.7. DEMOUTCC-----------φ SIGIN φ COMPIN– ()=pCC----------- Vr⁄()˙ .=
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
The frequency capture range (2fc) is defined as the
frequency range of input signals on which the PLL will lock
if it was initially out-of-lock. The frequency lock range
(2fL) is defined as the frequency range of input signals on
which the loop will stay locked if it was initially in lock. The
capture range is smaller or equal to the lock range.
With PC1, the capture range depends on the low-pass
filter characteristics and can be made as large as the lock
range.
This configuration retains lock even with very noisy input
signals. Typical behaviour of this type of phase
comparator is that it can lock to input frequencies close to
the harmonics of the VCO centre frequency.
Phase comparator 2 (PC2)
This is a positive edge-triggered phase and frequency
detector. When the PLL is using this comparator, the loop
is controlled by positive signal transitions and the duty
factors of SIGIN and COMPIN are not important. PC2
comprises two D-type flip-flops, control-gating and a
3-state output stage. The circuit functions as an up-down
counter (Fig.5) where SIGIN causes an up-count and
COMPIN a down-count. The transfer function of PC2,
assuming ripple (fr =fi) is suppressed,
is:
where VDEMOUT is the demodulator output at pin 10;
VDEMOUT =VPC2OUT (via low-pass filter).
The phase comparator gain is:
VDEMOUT is the resultant of the initial phase differences of
SIGIN and COMPIN as shown in Fig.8. Typical waveforms
for the PC2 loop locked at fo are shown in Fig.9.
When the frequencies of SIGIN and COMPIN are equal but
the phase of SIGIN leads that of COMPIN, the p-type
output driver at PC2OUT is held “ON” for a time
corresponding to the phase difference (φDEMOUT). When
the phase of SIGIN lags that of COMPIN, the n-type driver
is held “ON”.
When the frequency of SIGIN is higher than that of
COMPIN, the p-type output driver is held “ON” for most of
the input signal cycle time, and for the remainder of the
cycle both n and p- type drivers are ”OFF” (3-state). If the
SIGIN frequency is lower than the COMPIN frequency, then
it is the n-type driver that is held “ON” for most of the cycle.
Subsequently, the voltage at the capacitor (C2) of the
low-pass filter connected to PC2OUT varies until the signal DEMOUTCC-----------φ SIGINφ COMPIN– ()=pCC----------- Vr⁄().=
and comparator inputs are equal in both phase and
frequency. At this stable point the voltage on C2 remains
constant as the PC2 output is in 3-state and the VCO input
at pin 9 is a high impedance. Also in this condition, the
signal at the phase comparator pulse output (PCPOUT) is a
HIGH level and so can be used for indicating a locked
condition.
Thus, for PC2, no phase difference exists between
SIGIN and COMPIN over the full frequency range of the
VCO. Moreover, the power dissipation due to the low-pass
filter is reduced because both p and n-type drivers are
“OFF” for most of the signal input cycle. It should be noted
that the PLL lock range for this type of phase comparator
is equal to the capture range and is independent of the
low-pass filter. With no signal present at SIGIN the
VCO adjusts, via PC2, to its lowest frequency.
Phase comparator 3 (PC3)
This is a positive edge-triggered sequential phase detector
using an RS-type flip-flop. When the PLL is using this
comparator, the loop is controlled by positive signal
transitions and the duty factors of SIGIN and COMPIN are
not important. The transfer characteristic of PC3,
assuming ripple (fr =fi) is suppressed,
is:
where VDEMOUT is the demodulator output at pin 10;
VDEMOUT =VPC3OUT (via low-pass filter).
The phase comparator gain is:
The average output from PC3, fed to the VCO via the
low-pass filter and seen at the demodulator output at
pin 10 (VDEMOUT), is the resultant of the phase differences
of SIGIN and COMPIN as shown in Fig.10. Typical
waveforms for the PC3 loop locked at fo are shown in
Fig.11.
The phase-to-output response characteristic of PC3
(Fig.10) differs from that of PC2 in that the phase angle
between SIGIN and COMPIN varies between 0° and
360° and is 180° at the centre frequency. Also PC3 gives
a greater voltage swing than PC2 for input phase
differences but as a consequence the ripple content of the
VCO input signal is higher. The PLL lock range for this type
of phase comparator and the capture range are dependent
on the low-pass filter. With no signal present at SIGIN the
VCO adjusts, via PC3, to its lowest frequency. DEMOUTCC-----------φ SIGIN φ COMPIN– ()=pCC----------- Vr⁄().=
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
QUICK REFERENCE DATAGND=0 V; Tamb =25°C
Notes CPD is used to determine the dynamic power dissipation (PDin μW): =CPD× VCC2×fi+∑ (CL× VCC2×fo) where:= input frequency in MHz.= output frequency in MHz.= output load capacitance in pF.
VCC= supply voltage inV. (CL× VCC2×fo)= sum of outputs. Applies to the phase comparator section only (VCO disabled). For power dissipation of the VCO and demodulator
sections see Figs 22,23 and 24.
ORDERING INFORMATIONSee “74HC/HCT/HCU/HCMOS Logic Package Information”.
APPLICATIONS FM modulation and demodulation Frequency synthesis and multiplication Frequency discrimination Tone decoding Data synchronization and conditioning Voltage-to-frequency conversion Motor-speed control.
PACKAGE OUTLINESSee “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
PIN DESCRIPTION
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT
RATINGSLimiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground=0V)
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
DC CHARACTERISTICS FOR 74HC
Quiescent supply currentVoltages are referenced to GND (ground=0V)
Phase comparator sectionVoltages are referenced to GND (ground=0V)
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
VCO sectionVoltages are referenced to GND (ground=0V)
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
Note The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/ or
R2 are/is> 10 kΩ.
Demodulator sectionVoltages are referenced to GND (ground=0V)
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
AC CHARACTERISTICS FOR 74HC
Phase comparator sectionGND=0 V; tr =tf= 6 ns; CL= 50 pF
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
VCO sectionGND=0 V; tr =tf= 6 ns; CL= 50 pF
DC CHARACTERISTICS FOR 74HCT
Quiescent supply currentVoltages are referenced to GND (ground=0V)
Note The value of additional quiescent supply current (ΔICC) for a unit load of 1 is given above.
To determine ΔICC per input, multiply this value by the unit load coefficient shown in the table below.
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
DC CHARACTERISTICS FOR 74HCT
Phase comparator sectionVoltages are referenced to GND (ground=0V)
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
DC CHARACTERISTICS FOR 74HCT
VCO sectionVoltages are referenced to GND (ground=0V)
Note The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2
are/is> 10 kΩ.
Philips Semiconductors Product specification
Phase-locked-loop with VCO 74HC/HCT4046A
DC CHARACTERISTICS FOR 74HCT
Demodulator sectionVoltages are referenced to GND (ground=0V)
AC CHARACTERISTICS FOR 74HCT
Phase comparator sectionGND=0 V; tr =tf= 6 ns; CL= 50 pF
