74HC4024DB-74HC4024N-74HC4024PW Fast Delivery |IC PHOENIX CO.,LIMITED

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74HC4024DB-74HC4024N-74HC4024PW
74HC4024; 7-stage binary ripple counter
General descriptionThe 74HC4024isa high-speed Si-gate CMOS device andis pin compatible with the 4024
of the 4000B series. The 74HC4024 is speciﬁed in compliance with JEDEC
standard no. 7A.
The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0to
Q6).
The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP.
Each counter stage is a static toggle ﬂip-ﬂop.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: HBM EIA/JESD22-A114-B exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V. Multiple package options Speciﬁed from −40 °Cto+80 °C and from −40°Cto +125 °C. Applications Frequency dividing circuits Time delay circuits.
74HC4024
7-stage binary ripple counter
Philips Semiconductors 74HC4024 Quick reference data
[1] CPD is used to determine the dynamic power dissipation (PD in μW). =CPD× VCC2×fi× N+ ∑(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
∑(CL× VCC2×fo) = sum of outputs. Ordering information
Table 1: Quick reference data
GND=0 V; Tamb =25 °C; tr =tf= 6 ns.
tPHL, tPLH propagation delay CP to =15pF;
VCC =5V
-14 - ns
fmax maximum clock frequency CL =15pF;
VCC =5V 90 - MHz input capacitance - 3.5 - pF
CPD power dissipation
capacitance= GND to VCC [1] -25 - pF
Table 2: Ordering information
74HC4024N −40 °C to +125°C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC4024D −40 °C to +125°C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74HC4024DB −40 °C to +125°C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74HC4024PW −40 °C to +125°C TSSOP14 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT402-1
Philips Semiconductors 74HC4024 Functional diagram
Philips Semiconductors 74HC4024 Pinning information
7.1 Pinning
7.2 Pin description
Table 3: Pin description 1 clock input (HIGH-to-LOW, edge-triggered) 2 master reset input (active HIGH) 3 parallel output 6 4 parallel output 5 5 parallel output 4 6 parallel output 3
GND 7 ground (0V)
n.c. 8 not connected 9 parallel output 2
n.c. 10 not connected 11 parallel output 1 12 parallel output 0
n.c. 13 not connected
VCC 14 positive supply voltage
Philips Semiconductors 74HC4024 Functional description
8.1 Function table
[1]H= HIGH voltage level;= LOW voltage level; = don’t care;= LOW-to-HIGH clock transition; HIGH-to-LOW clock transition. Limiting values
[1] Above 70 °C: Ptot derates linearly with 12 mW/K.
[2] Above 70 °C: Ptot derates linearly with 8 mW/K.
Table 4: Function table[1] L ↑ no change count
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
VCC supply voltage −0.5 +7 V
IIK input diode current VI < −0.5 V or VI >VCC+ 0.5 V - ±20 mA
IOK output diode current VO< −0.5 V or >VCC+ 0.5V ±20 mA output source or sink
current
VO = −0.5 V to VCC+ 0.5V - ±25 mA
ICC, IGND VCC or GND current - ±50 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation
DIP14 package [1]- 750 mW
SO14, SSOP14 and
TSSOP14 packages
[2]- 500 mW
Philips Semiconductors 74HC4024
10. Recommended operating conditions
11. Static characteristics
Table 6: Recommended operating conditions
VCC supply voltage 2.0 5.0 6.0 V input voltage 0 - VCC V output voltage 0 - VCC V
tr, tf input rise andfall times
except CP
VCC = 2.0 V - - 1000 ns
VCC = 4.5 V - 6.0 500 ns
VCC = 6.0 V - - 400 ns
Tamb ambient temperature −40 - +125 °C
Table 7: Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb =25°C
VIH HIGH-level input voltage VCC= 2.0V 1.5 1.2 - V
VCC= 4.5V 3.15 2.4 - V
VCC= 6.0V 4.2 3.2 - V
VIL LOW-level input voltage VCC= 2.0V - 0.8 0.5 V
VCC= 4.5V - 2.1 1.35 V
VCC= 6.0V - 2.8 1.8 V
VOH HIGH-level output voltage VI =VIHorVIL= −20 μA; VCC= 2.0V 1.9 2.0 - V= −20 μA; VCC= 4.5V 4.4 4.5 - V= −20 μA; VCC= 6.0V 5.9 6.0 - V=−4 mA; VCC= 4.5V 3.98 4.32 - V= −5.2 mA; VCC= 6.0V 5.48 5.81 - V
VOL LOW-level output voltage VI =VIHorVIL =20 μA; VCC= 2.0V - 0 0.1 V =20 μA; VCC= 4.5V - 0 0.1 V =20 μA; VCC= 6.0V - 0 0.1 V=4 mA; VCC= 4.5V - 0.15 0.26 V= 5.2 mA; VCC= 6.0V - 0.16 0.26 V
ILI input leakage current VI =VCCor GND; VCC= 6.0V - - ±0.1 μA
ICC quiescent supply current VI =VCCor GND; IO=0 A; VCC= 6.0V - - 8.0 μA input capacitance - 3.5 - pF
Tamb= −40 °C to +85°C
VIH HIGH-level input voltage VCC= 2.0V 1.5 - - V
VCC= 4.5V 3.15 - - V
VCC= 6.0V 4.2 - - V
Philips Semiconductors 74HC4024
VIL LOW-level input voltage VCC= 2.0V - - 0.5 V
VCC= 4.5V - - 1.35 V
VCC= 6.0V - - 1.8 V
VOH HIGH-level output voltage VI =VIHorVIL= −20 μA; VCC= 2.0V 1.9 - - V= −20 μA; VCC= 4.5V 4.4 - - V= −20 μA; VCC= 6.0V 5.9 - - V=−4 mA; VCC= 4.5V 3.84 - - V= −5.2 mA; VCC= 6.0V 5.34 - - V
VOL LOW-level output voltage VI =VIHorVIL =20 μA; VCC= 2.0V - - 0.1 V =20 μA; VCC= 4.5V - - 0.1 V =20 μA; VCC= 6.0V - - 0.1 V=4 mA; VCC= 4.5V - - 0.33 V= 5.2 mA; VCC= 6.0V - - 0.33 V
ILI input leakage current VI =VCCor GND; VCC= 6.0V - - ±1.0 μA
ICC quiescent supply current VI =VCCor GND; IO=0 A; VCC= 6.0V - - 80 μA
Tamb= −40 °C to +125°C
VIH HIGH-level input voltage VCC= 2.0V 1.5 - - V
VCC= 4.5V 3.15 - - V
VCC= 6.0V 4.2 - - V
VIL LOW-level input voltage VCC= 2.0V - - 0.5 V
VCC= 4.5V - - 1.35 V
VCC= 6.0V - - 1.8 V
VOH HIGH-level output voltage VI =VIHorVIL= −20 μA; VCC= 2.0V 1.9 - - V= −20 μA; VCC= 4.5V 4.4 - - V= −20 μA; VCC= 6.0V 5.9 - - V=−4 mA; VCC= 4.5V 3.7 - - V= −5.2 mA; VCC= 6.0V 5.2 - - V
VOL LOW-level output voltage VI =VIHorVIL =20 μA; VCC= 2.0V - - 0.1 V =20 μA; VCC= 4.5V - - 0.1 V =20 μA; VCC= 6.0V - - 0.1 V=4 mA; VCC= 4.5V - - 0.4 V= 5.2 mA; VCC= 6.0V - - 0.4 V
ILI input leakage current VI =VCCor GND; VCC= 6.0V - - ±1.0 μA
ICC quiescent supply current VI =VCCor GND; IO=0 A; VCC= 6.0V - - 160 μA
Table 7: Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Philips Semiconductors 74HC4024
12. Dynamic characteristics
Table 8: Dynamic characteristics
GND= 0 V; tr=tf= 6 ns; CL= 50 pF; see Figure7.
Tamb = 25°C
tPHL, tPLH propagation delay CP to Q0 see Figure6
VCC = 2.0 V - 47 175 ns
VCC = 4.5 V - 17 35 ns
VCC = 6.0 V - 14 30 ns
VCC= 5.0 V; CL =15pF - 14 - ns
propagation delay Qn to Qn+1 see Figure6
VCC = 2.0 V - 25 80 ns
VCC = 4.5 V - 9 16 ns
VCC = 6.0 V - 7 14 ns
tPHL propagation delay MR to Q0 see Figure6
VCC = 2.0 V - 63 200 ns
VCC = 4.5 V - 23 40 ns
VCC = 6.0 V - 18 34 ns
tTHL, tTLH output transition time see Figure6
VCC = 2.0 V - 19 75 ns
VCC = 4.5 V - 7 15 ns
VCC = 6.0 V - 6 13 ns CP clock pulse width HIGH or
LOW
see Figure6
VCC = 2.0 V 80 17 - ns
VCC = 4.5 V 16 6 - ns
VCC = 6.0 V 14 5 - ns
MR master reset pulse width
HIGH
see Figure6
VCC = 2.0 V 80 22 - ns
VCC = 4.5 V 16 8 - ns
VCC = 6.0 V 14 6 - ns
trem removal time MR to CP see Figure6
VCC = 2.0 V 50 6 - ns
VCC = 4.5 V 10 2 - ns
VCC = 6.0 V 9 2 - ns
fmax maximum clock frequency see Figure6
VCC = 2.0 V 6.0 27 - MHz
VCC = 4.5 V 30 82 - MHz
VCC = 6.0 V 35 98 - MHz
VCC= 5.0 V; CL=15pF - 90 - MHz
CPD power dissipation capacitance VI= GND to VCC [1] -25 - pF
Philips Semiconductors 74HC4024
Tamb = −40 °C to +85°C
tPHL, tPLH propagation delay CP to Q0 see Figure6
VCC = 2.0 V - - 220 ns
VCC = 4.5 V - - 44 ns
VCC = 6.0 V - - 37 ns
propagation delay Qn to Qn+1 see Figure6
VCC = 2.0 V - - 100 ns
VCC = 4.5 V - - 20 ns
VCC = 6.0 V - - 17 ns
tPHL propagation delay MR to Q0 see Figure6
VCC = 2.0 V - - 250 ns
VCC = 4.5 V - - 50 ns
VCC = 6.0 V - - 43 ns
tTHL, tTLH output transition time see Figure6
VCC = 2.0 V - - 95 ns
VCC = 4.5 V - - 19 ns
VCC = 6.0 V - - 16 ns CP clock pulse width HIGH or
LOW
see Figure6
VCC = 2.0 V 100 - - ns
VCC = 4.5 V 20 - - ns
VCC = 6.0 V 17 - - ns
MR master reset pulse width
HIGH
see Figure6
VCC = 2.0 V 100 - - ns
VCC = 4.5 V 20 - - ns
VCC = 6.0 V 17 - - ns
trem removal time MR to CP see Figure6
VCC = 2.0 V 65 - - ns
VCC = 4.5 V 13 - - ns
VCC = 6.0 V 11 - - ns
fmax maximum clock frequency see Figure6
VCC = 2.0 V 4.8 - - MHz
VCC = 4.5 V 24 - - MHz
VCC = 6.0 V 28 - - MHz
Table 8: Dynamic characteristics …continued
GND= 0 V; tr=tf= 6 ns; CL= 50 pF; see Figure7.

Partno	Mfg	Dc	Qty	Available	Descript
74HC4024DB	PHILIPS	N/a	26	avai	74HC4024; 7-stage binary ripple counter
74HC4024N	PHI	N/a	54	avai	74HC4024; 7-stage binary ripple counter
74HC4024PW	PHILIPS	N/a	1349	avai	7-stage binary ripple counter