74HC4024D Fast Delivery |IC PHOENIX CO.,LIMITED

74HC4024D ,7-stage binary ripple counterGeneral descriptionThe 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an over ..
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74HC4024D
7-stage binary ripple counter
1. General description
The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to
Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears
all counter stages and forces all outputs LOW, independent of the state of CP. Each
counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the
circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits Low-power dissipation Complies with JEDEC standard no.7A ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V. Multiple package options Specified from 40 Cto+80 C and from 40 Cto+125 C.
3. Applications Frequency dividing circuits Time delay circuits.
74HC4024
7-stage binary ripple counter
Rev. 7 — 31 October 2013 Product data sheet
NXP Semiconductors 74HC4024
7-stage binary ripple counter
4. Ordering information
5. Functional diagram
Table 1. Ordering information
74HC4024N 40 C to +125C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC4024D 40 C to +125C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74HC4024DB 40 C to +125C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74HC4024PW 40 C to +125C TSSOP14 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT402-1
NXP Semiconductors 74HC4024
7-stage binary ripple counter
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H= HIGH voltage level;= LOW voltage level; = don’t care;= LOW-to-HIGH clock transition;
= HIGH-to-LOW clock transition.
Table 2. Pin description 1 clock input (HIGH-to-LOW, edge-triggered) 2 master reset input (active HIGH)
Q6, Q5, Q4, Q3, Q2, Q2, Q1, Q0 3, 4, 5, 6, 9, 11, 12 parallel output
GND 7 ground (0V)
n.c. 8, 10, 13 not connected
VCC 14 positive supply voltage
Table 3. Function table[1] L  no change count
NXP Semiconductors 74HC4024
7-stage binary ripple counter
8. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[3] For (T)SSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60C.
9. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V - 20 mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V - 20 mA output current VO = 0.5 V to VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation DIP14 package [1]- 750 mW
SO14 package [2]- 500 mW
SSOP14 and TSSOP14 package [3]- 500 mW
Table 5. Recommended operating conditions
VCC supply voltage 2.0 5.0 6.0 V input voltage 0 - VCC V output voltage 0 - VCC V
t/V input transition rise and fall
rate
VCC = 2.0 V - - 625 ns/V
VCC = 4.5 V - 1.67 139 ns/V
VCC = 6.0 V - - 83 ns/V
Tamb ambient temperature 40 - +125 C
NXP Semiconductors 74HC4024
7-stage binary ripple counter
10. Static characteristicsTable 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb =25C
VIH HIGH-level input voltage VCC= 2.0V 1.5 1.2 - V
VCC= 4.5V 3.15 2.4 - V
VCC= 6.0V 4.2 3.2 - V
VIL LOW-level input voltage VCC =2.0V - 0.8 0.5 V
VCC =4.5V - 2.1 1.35 V
VCC =6.0V - 2.8 1.8 V
VOH HIGH-level output voltage VI =VIHorVIL= 20 A; VCC =2.0V 1.9 2.0 - V= 20 A; VCC =4.5V 4.4 4.5 - V= 20 A; VCC =6.0V 5.9 6.0 - V= 4mA; VCC= 4.5V 3.98 4.32 - V= 5.2 mA; VCC= 6.0V 5.48 5.81 - V
VOL LOW-level output voltage VI =VIHorVIL =20 A; VCC =2.0V - 0 0.1 V =20 A; VCC =4.5V - 0 0.1 V =20 A; VCC =6.0V - 0 0.1 V =4mA; VCC= 4.5V - 0.15 0.26 V =5.2 mA; VCC= 6.0V - 0.16 0.26 V input leakage current VI =VCCor GND; VCC =6.0V - - 0.1 A
ICC supply current VI =VCCor GND; IO =0A; VCC= 6.0V - - 8.0 A input capacitance - 3.5 - pF
Tamb= 40 C to +85C
VIH HIGH-level input voltage VCC= 2.0V 1.5 - - V
VCC= 4.5V 3.15 - - V
VCC= 6.0V 4.2 - - V
VIL LOW-level input voltage VCC= 2.0V --0.5 V
VCC= 4.5V --1.35 V
VCC= 6.0V --1.8 V
VOH HIGH-level output voltage VI =VIHorVIL= 20 A; VCC= 2.0V 1.9 --V= 20 A; VCC= 4.5V 4.4 --V= 20 A; VCC= 6.0V 5.9 --V= 4mA; VCC= 4.5V 3.84 - - V= 5.2 mA; VCC= 6.0V 5.34 - - V
NXP Semiconductors 74HC4024
7-stage binary ripple counter
VOL LOW-level output voltage VI =VIHorVIL =20 A; VCC= 2.0V --0.1 V =20 A; VCC= 4.5V --0.1 V =20 A; VCC= 6.0V --0.1 V =4mA; VCC= 4.5V - - 0.33 V =5.2 mA; VCC= 6.0V - - 0.33 V input leakage current VI =VCCor GND; VCC =6.0V - - 1.0 A
ICC supply current VI =VCCor GND; IO =0A; VCC= 6.0V --80 A
Tamb= 40 C to +125C
VIH HIGH-level input voltage VCC= 2.0V 1.5 - - V
VCC= 4.5V 3.15 - - V
VCC= 6.0V 4.2 - - V
VIL LOW-level input voltage VCC= 2.0V --0.5 V
VCC= 4.5V --1.35 V
VCC= 6.0V --1.8 V
VOH HIGH-level output voltage VI =VIHorVIL= 20 A; VCC= 2.0V 1.9 --V= 20 A; VCC= 4.5V 4.4 --V= 20 A; VCC= 6.0V 5.9 --V= 4mA; VCC= 4.5V 3.7 - - V= 5.2 mA; VCC= 6.0V 5.2 - - V
VOL LOW-level output voltage VI =VIHorVIL =20 A; VCC= 2.0V --0.1 V =20 A; VCC= 4.5V --0.1 V =20 A; VCC= 6.0V --0.1 V =4mA; VCC= 4.5V - - 0.4 V =5.2 mA; VCC= 6.0V - - 0.4 V input leakage current VI =VCCor GND; VCC =6.0V - - 1.0 A
ICC supply current VI =VCCor GND; IO =0A; VCC= 6.0V --160 A
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC4024
7-stage binary ripple counter
11. Dynamic characteristicsTable 7. Dynamic characteristics
GND= 0 V; tr=tf =6 ns; CL= 50 pF; see Figure7.
Tamb = 25 C
tpd propagation delay CP to Q0; see Figure6 [1]
VCC = 2.0 V - 47 175 ns
VCC = 4.5 V - 17 35 ns
VCC = 6.0 V - 14 30 ns
VCC =5.0 V; CL =15pF - 14 - ns
Qn to Qn+1; see Figure6 [1]
VCC = 2.0 V - 25 80 ns
VCC = 4.5 V - 9 16 ns
VCC = 6.0 V - 7 14 ns
tPHL HIGH to LOW
propagation delay
MR to Q0; see Figure6
VCC = 2.0 V - 63 200 ns
VCC = 4.5 V - 23 40 ns
VCC = 6.0 V - 18 34 ns transition time see Figure6 [2]
VCC = 2.0 V - 19 75 ns
VCC = 4.5 V - 7 15 ns
VCC = 6.0 V - 6 13 ns pulse width CP HIGH or LOW; see Figure6
VCC = 2.0 V 8017- ns
VCC = 4.5 V 16 6 - ns
VCC = 6.0 V 14 5 - ns
MR HIGH; see Figure6
VCC = 2.0 V 8022- ns
VCC = 4.5 V 16 8 - ns
VCC = 6.0 V 14 6 - ns
trec recovery time MR to CP; see Figure6
VCC = 2.0 V 50 6 - ns
VCC = 4.5 V 10 2 - ns
VCC = 6.0 V 9 2 - ns
fmax maximum frequency CP; see Figure6
VCC = 2.0 V 6.0 27 - MHz
VCC = 4.5 V 3082- MHz
VCC = 6.0 V 3598- MHz
VCC =5.0 V; CL =15pF - 90 - MHz
CPD power dissipation
capacitance = GND to VCC [3] -25 -pF
NXP Semiconductors 74HC4024
7-stage binary ripple counter
Tamb = 40 C to +85 C
tpd propagation delay CP to Q0; see Figure6 [1]
VCC = 2.0 V - - 220 ns
VCC = 4.5 V --44 ns
VCC = 6.0 V --37 ns
Qn to Qn+1; see Figure6 [1]
VCC = 2.0 V - - 100 ns
VCC = 4.5 V --20 ns
VCC = 6.0 V --17 ns
tPHL HIGH to LOW
propagation delay
MR to Q0; see Figure6
VCC = 2.0 V - - 250 ns
VCC = 4.5 V --50 ns
VCC = 6.0 V --43 ns transition time see Figure6 [2]
VCC = 2.0 V --95 ns
VCC = 4.5 V --19 ns
VCC = 6.0 V --16 ns pulse width CP HIGH or LOW; see Figure6
VCC = 2.0 V 100 - - ns
VCC = 4.5 V 20 --ns
VCC = 6.0 V 17 --ns
MR HIGH; see Figure6
VCC = 2.0 V 100 - - ns
VCC = 4.5 V 20 --ns
VCC = 6.0 V 17 --ns
trec recovery time MR to CP; see Figure6
VCC = 2.0 V 65 --ns
VCC = 4.5 V 13 --ns
VCC = 6.0 V 11 --ns
fmax maximum frequency CP; see Figure6
VCC = 2.0 V 4.8 --MHz
VCC = 4.5 V 24 --MHz
VCC = 6.0 V 28 --MHz
Table 7. Dynamic characteristics …continued
GND= 0 V; tr=tf =6 ns; CL= 50 pF; see Figure7.
NXP Semiconductors 74HC4024
7-stage binary ripple counter
Tamb = 40 C to +125 C
tpd propagation delay CP to Q0; see Figure6 [1]
VCC = 2.0 V - - 265 ns
VCC = 4.5 V --53 ns
VCC = 6.0 V --45 ns
Qn to Qn+1; see Figure6 [1]
VCC = 2.0 V - - 120 ns
VCC = 4.5 V --24 ns
VCC = 6.0 V --20 ns
tPHL HIGH to LOW
propagation delay
MR to Q0; see Figure6
VCC = 2.0 V - - 300 ns
VCC = 4.5 V --60 ns
VCC = 6.0 V --51 ns transition time see Figure6 [2]
VCC = 2.0 V - - 110 ns
VCC = 4.5 V --22 ns
VCC = 6.0 V --19 ns pulse width CP HIGH or LOW; see Figure6
VCC = 2.0 V 120 - - ns
VCC = 4.5 V 24 --ns
VCC = 6.0 V 20 --ns
MR HIGH; see Figure6
VCC = 2.0 V 120 - - ns
VCC = 4.5 V 24 --ns
VCC = 6.0 V 20 --ns
trec recovery time MR to CP; see Figure6
VCC = 2.0 V 75 --ns
VCC = 4.5 V 15 --ns
VCC = 6.0 V 13 --ns
Table 7. Dynamic characteristics …continued
GND= 0 V; tr=tf =6 ns; CL= 50 pF; see Figure7.
NXP Semiconductors 74HC4024
7-stage binary ripple counter
[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2 fo) = sum of outputs.
12. Waveforms
fmax maximum frequency CP; see Figure6
VCC = 2.0 V 4.0 --MHz
VCC = 4.5 V 20 --MHz
VCC = 6.0 V 24 --MHz
Table 7. Dynamic characteristics …continued
GND= 0 V; tr=tf =6 ns; CL= 50 pF; see Figure7.

Partno	Mfg	Dc	Qty	Available	Descript
74HC4024D	NXP ?	N/a	40000	avai	7-stage binary ripple counter