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74HC4020N
14-stage binary ripple counter
1. General description
The 74HC4020; 74HCT4020 are high-speed Si-gate CMOS devices and are pin
compatible with the HEF4020B series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC4020; 74HCT4020 are 14-stage binary ripple counters with a clock input (CP),
an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0, Q3
to Q13). The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP.
Each counter stage is a static toggle flip-flop.
2. Features and benefits Multiple package options Complies with JEDEC standard no. 7A Specified from 40 Cto+85 C and from 40 Cto+125C
3. Applications Frequency dividing circuits Time delay circuits Control counters
4. Ordering information
74HC4020; 74HCT4020
14-stage binary ripple counter
Rev. 5 — 6 August 2012 Product data sheet
Table 1. Ordering information
74HC4020N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT4020N
74HC4020D 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HCT4020D
74HC4020DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body
width 5.3 mm
SOT338-1
74HCT4020DB
NXP Semiconductors 74HC4020; 74HCT4020
14-stage binary ripple counter
5. Functional diagram
74HC4020PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT4020PW
74HC4020BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5  3.5  0.85 mm
SOT763-1
74HCT4020BQ
Table 1. Ordering information …continued
NXP Semiconductors 74HC4020; 74HCT4020
14-stage binary ripple counter
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin description
Q0, Q3 to Q13 9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3 output
GND 8 ground (0 V) 10 clock input (HIGH-to-LOW, edge-triggered) 11 master reset input (active HIGH)
VCC 16 positive supply voltage
NXP Semiconductors 74HC4020; 74HCT4020
14-stage binary ripple counter
7. Functional description
[1] H= HIGH voltage level; L= LOW voltage level; X= don’t care; = LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition.
7.1 Timing diagram
Table 3. Function table L no change L count L
NXP Semiconductors 74HC4020; 74HCT4020
14-stage binary ripple counter
8. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
9. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI > VCC +0.5V - 20 mA
IOK output clamping current VI < 0.5 V or VI > VCC +0.5 V - 20 mA output current 0.5 V < VO < VCC+ 0.5 V - 25 mA
ICC supply current - 50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125C [1]
DIP16 package - 750 mW
SO16, SSOP16, TSSOP16 and
DHVQFN16 packages
-500 mW
Table 5. Recommended operating conditions
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
t/V input transition rise and
fall rate
except for
Schmitt trigger inputs
VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
NXP Semiconductors 74HC4020; 74HCT4020
14-stage binary ripple counter
10. Static characteristicsTable 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC4020
VIH HIGH-level
input voltage
VCC = 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC = 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC =6.0V 0.1 - 1- 1 A
ICC supply current VI = VCC or GND; IO =0A;
VCC =6.0V - 8.0 - 80 - 160 A input
capacitance
-3.5 - - - - - pF
74HCT4020
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = 20A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = 20 A; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5V - 0.15 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC =5.5V 0.1 - 1- 1 A
NXP Semiconductors 74HC4020; 74HCT4020
14-stage binary ripple counter
11. Dynamic characteristics
ICC supply current VI = VCC or GND; IO =0A;
VCC =5.5V - 8.0 - 80 - 160 A
ICC additional
supply current =VCC 2.1 V; IO =0A;
other inputs at VCC or GND;
VCC= 4.5Vto 5.5V
pin MR - 110 396 - 495 - 539 A
pin CP - 85 306 - 383 - 417 A input
capacitance
-3.5 - - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Table 7. Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure10
74HC4020
tpd propagation
delay
CP to Q0; see Figure8 [1]
VCC = 2.0 V; CL=50pF - 39 140 - 175 - 210 ns
VCC = 4.5 V; CL=50pF - 14 28 - 35 - 42 ns
VCC = 5.0 V; CL =15pF - 11 - - - - - ns
VCC = 6.0 V; CL=50pF - 11 24 - 30 - 36 ns
Qn to Qn+1; see Figure9
VCC = 2.0 V; CL =50pF - 22 75 - 95 - 110 ns
VCC = 4.5 V; CL =50pF - 8 15 - 19 - 22 ns
VCC = 5.0 V; CL =15pF - 6 - - - - - ns
VCC = 6.0 V; CL =50pF - 6 13 - 16 - 19 ns
tPHL HIGH to LOW
propagation
delay
MR to Qn; see Figure8
VCC =2.0 V; CL=50pF - 55 170 - 215 - 225 ns
VCC = 4.5 V; CL=50pF - 20 34 - 43 - 51 ns
VCC = 5.0 V; CL =15pF - 17 - - - - - ns
VCC = 6.0 V; CL=50pF - 16 29 - 37 - 43 ns transition
time
Qn; see Figure8 [2]
VCC = 2.0 V; CL =50pF - 19 75 - 95 - 110 ns
VCC = 4.5 V; CL =50pF - 7 15 - 19 - 22 ns
VCC = 6.0 V; CL =50pF - 6 13 - 16 - 19 ns
NXP Semiconductors 74HC4020; 74HCT4020
14-stage binary ripple counter pulse width CP HIGH or LOW;
see Figure8
VCC = 2.0 V; CL=50pF 80 14 - 100 - 120 - ns
VCC = 4.5 V; CL =50pF 16 4 - 20 - 24 - ns
VCC = 6.0 V; CL =50pF 14 3 - 17 - 20 - ns
MR HIGH; see Figure8
VCC = 2.0 V; CL=50pF 80 17 - 100 - 120 - ns
VCC = 4.5 V; CL =50pF 16 6 - 20 - 24 - ns
VCC = 6.0 V; CL =50pF 14 5 - 17 - 20 - ns
trec recovery time MR to CP; see Figure8
VCC = 2.0 V; CL =50pF 50 6 - 65 - 75 - ns
VCC = 4.5 V; CL =50pF 10 2 - 13 - 15 - ns
VCC = 6.0 V; CL =50pF 9 2 - 11 - 13 - ns
fmax maximum
frequency
see Figure8
VCC = 2.0 V; CL=50pF 6.0 30 - 4.8 - 4.0 - MHz
VCC = 4.5 V; CL =50pF 30 92 - 24 - 20 - MHz
VCC = 5.0 V; CL= 15 pF - 101 - - - - - MHz
VCC = 6.0 V; CL=50pF 35 109 - 28 - 24 - MHz
CPD power
dissipation
capacitance
[3] -19- - - - - pF
74HCT4020
tpd propagation
delay
CP to Q0; see Figure8 [1]
VCC = 4.5 V; CL=50pF - 18 36 - 45 - 54 ns
VCC = 5.0 V; CL= 15 pF - 15 - - - - - ns
Qn to Qn+1; see Figure9
VCC = 4.5 V; CL =50pF - 8 15 - 19 - 22 ns
VCC = 5.0 V; CL =15pF - 6 - - - - - ns
tPHL HIGH to LOW
propagation
delay
MR to Qn; see Figure8
VCC = 4.5 V; CL=50pF - 22 45 - 56 - 68 ns
VCC = 5.0 V; CL =15pF - 19 - - - - - ns transition
time
Qn; see Figure8 [2]
VCC = 4.5 V; CL =50pF - 7 15 - 19 - 22 ns pulse width CP HIGH or LOW;
see Figure8
VCC = 4.5 V; CL =50pF 20 7 - 25 - 30 - ns
MR HIGH; see Figure8
VCC = 4.5 V; CL =50pF 20 8 - 25 - 30 - ns
trec recovery time MR to CP; see Figure8
VCC = 4.5 V; CL =50pF 10 2 - 13 - 15 - ns
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure10
NXP Semiconductors 74HC4020; 74HCT4020
14-stage binary ripple counter
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC 2  fi + (CL  VCC 2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
 (CL  VCC 2  fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
12. Waveforms
fmax maximum
frequency
see Figure8
VCC = 4.5 V; CL =50pF 25 47 - 20 - 17 - MHz
VCC = 5.0 V; CL =15pF - 52 - - - - - MHz
CPD power
dissipation
capacitance
[3] -20- - - - - pF
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure10
NXP Semiconductors 74HC4020; 74HCT4020
14-stage binary ripple counter
Table 8. Measurement points
74HC4020 0.5 VCC 0.5 VCC
74HCT4020 1.3V 1.3 V

Partno	Mfg	Dc	Qty	Available	Descript
74HC4020N	TI	N/a	56	avai	14-stage binary ripple counter
74HC4020N	NSC	N/a	125	avai	14-stage binary ripple counter