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74HC4017DNXPN/a100avaiJohnson decade counter with 10 decoded outputs
74HC4017PWNXP ?N/a1955avai74HC/HCT4017; Johnson decade counter with 10 decoded outputs


74HC4017PW ,74HC/HCT4017; Johnson decade counter with 10 decoded outputsFeatures and benefits Wide supply voltage range from 2.0 V to 6.0 V Input levels: For 74HC4017: ..
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74HC4017D-74HC4017PW
Johnson decade counter with 10 decoded outputs
1. General description
The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded
outputs (Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs
(CP0 and CP1) and an overriding asynchronous master reset input (MR). The counter is
advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a
HIGH-to-LOW transition at CP1 while CP0 is HIGH. When cascading counters, the Q5-9
output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive
the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 =
HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and CP1). Automatic code
correction of the counter is provided by an internal circuit: following any illegal code the
counter returns to a proper counting mode within 11 clock pulses. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
2. Features and benefits Wide supply voltage range from 2.0 Vto 6.0V Input levels: For 74HC4017: CMOS level For 74HCT4017: TTL level Complies with JEDEC standard no. 7 A ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125C
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Rev. 4 — 10 December 2013 Product data sheet
NXP Semiconductors 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
3. Ordering information
4. Functional diagram
Table 1. Ordering information
74HC4017
74HC4017N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HC4017D 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HC4017DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HC4017PW 40 Cto+125C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HC4017BQ 40 Cto+125C DHVQFN16 plastic dual in-line compatible thermal-enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 3.5  0.85 mm
SOT763-1
74HCT4017
74HCT4017N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT4017D 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HCT4017BQ 40 Cto+125C DHVQFN16 plastic dual in-line compatible thermal-enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 3.5  0.85 mm
SOT763-1
NXP Semiconductors 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
NXP Semiconductors 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
NXP Semiconductors 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description
Q[0:9] 3, 2, 4, 7, 10, 1, 5, 6, 9, 11 decoded output
GND 8 ground (0V)
Q5-9 12 carry output (active LOW)
CP1 13 clock input (HIGH-to-LOW edge-triggered)
CP0 14 clock input (LOW-to-HIGH edge-triggered) 15 master reset input (active HIGH)
VCC 16 supply voltage
NXP Semiconductors 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
6. Functional description
[1] H= HIGH voltage level;= LOW voltage level;= don’t care;= LOW-to-HIGH transition;= HIGH-to-LOW transition;
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 12 mW/K above 70C.
[3] Ptot derates linearly with 8 mW/K above 70C.
[4] Ptot derates linearly with 5.5 mW/K above 60C.
[5] Ptot derates linearly with 4.5 mW/K above 60C.
Table 3. Function table[1] X Q0 = Q5-9 = HIGH; toQ9 = LOW  counter advances  L counter advances L X no change X H no change  no change  L no change
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V [1]- 20 mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V [1]- 20 mA output current 0.5 V < VO < VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125C
DIP16 package [2]- 750 mW
SO16 package [3]- 500 mW
(T)SSOP16 package [4]- 500 mW
DHVQFN16 package [5]- 500 mW
NXP Semiconductors 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
74HC4017
VCC supply voltage 2.0 5.0 6.0 V input voltage 0 - VCC V output voltage 0 - VCC V
t/V input transition rise and fall rate VCC = 2.0 V - - 625 ns/V
VCC = 4.5 V - 1.67 139 ns/V
VCC = 6.0 V - - 83 ns/V
Tamb ambient temperature 40 - +125 C
74HCT4017
VCC supply voltage 4.5 5.0 5.5 V input voltage 0 - VCC V output voltage 0 - VCC V
t/V input transition rise and fall rate VCC = 4.5 V - 1.67 139 ns/V
Tamb ambient temperature 40 - +125 C
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC4017
VIH HIGH-level
input voltage
VCC= 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC= 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC= 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC= 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC= 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC= 6.0V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage =VIHor VIL= 20 A; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= 20 A; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= 20 A; VCC= 6.0V 5.9 6.0 - 5.9 - 5.9 - V= 4.0 mA; VCC= 4.5V 3.98 4.32 - 3.84 - 3.7 - V= 5.2 mA; VCC= 6.0V 5.48 5.81 - 5.34 - 5.2 - V
NXP Semiconductors 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
VOL LOW-level
output voltage =VIHor VIL =20 A; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V =20 A; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V =20 A; VCC= 6.0V - 0 0.1 - 0.1 - 0.1 V =4.0 mA; VCC= 4.5V - 0.15 0.26 - 0.33 - 0.4 V =5.2 mA; VCC= 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =6.0V 0.1 - 1.0 - 1.0 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =6.0V - 8.0 - 80 - 160 A input
capacitance
-3.5 - - - - - pF
74HCT4017
VIH HIGH-level
input voltage
VCC= 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC= 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage =VIHor VIL; VCC =4.5V= 20A 4.4 4.5 - 4.4 - 4.4 - V=4 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage =VIHor VIL; VCC =4.5V =20A - 0 0.1 - 0.1 - 0.1 V= 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =5.5V 0.1 - 1.0 - 1.0 A
ICC supply current VI =VCCor GND;
VCC =5.5 V; IO =0A - 8.0 - 80 - 160 A
ICC additional
supply current
per input pin; =VCC 2.1V;
other inputs at VCCor GND;
VCC= 4.5Vto 5.5V; =0A
CP0 input - 25 90 - 113 - 123 A
CP1 input - 40 144 - 180 - 196 A
MR input - 50 180 - 225 - 245 A input
capacitance
-3.5 - - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
10. Dynamic characteristicsTable 7. Dynamic characteristics
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure11.
74HC4017
tpd propagation
delay
CP0 to Qn; CP0 to Q5-9;
see Figure10
[1]
VCC = 2.0 V - 63 230 - 290 - 345 ns
VCC = 4.5 V - 23 46 - 58 - 69 ns
VCC = 5.0 V; =15pF
-20 - - - - - ns
VCC = 6.0 V - 18 39 - 49 - 59 ns
CP1 to Qn; CP1 to Q5-9;
see Figure10
VCC = 2.0 V - 61 250 - 315 - 375 ns
VCC = 4.5 V - 22 50 - 63 - 75 ns
VCC = 5.0 V; =15pF
-20 - - - - - ns
VCC = 6.0 V - 18 43 - 54 - 64 ns
tPHL HIGH to LOW
propagation
delay
MR to Q[1:9];
see Figure10
VCC = 2.0 V - 52 230 - 290 - 345 ns
VCC = 4.5 V - 19 46 - 58 - 69 ns
VCC = 6.0 V - 15 39 - 49 - 59 ns
tPLH LOW to HIGH
propagation
delay
MR to Q5-9, Q0;
see Figure10
VCC = 2.0 V - 55 230 - 290 - 345 ns
VCC = 4.5 V - 20 46 - 58 - 69 ns
VCC = 6.0 V - 16 39 - 49 - 59 ns transition time see Figure10 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns pulse width CP0 and CP1 (HIGH or
LOW); see Figure9
VCC = 2.0 V 80 17 - 100 - 120 - ns
VCC = 4.5 V 16 6 - 20 - 24 - ns
VCC = 6.0 V 14 5 - 17 - 20 - ns
MR (HIGH); see Figure9
VCC = 2.0 V 80 19 - 100 - 120 - ns
VCC = 4.5 V 16 7 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
NXP Semiconductors 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
tsu set-up time CP1toCP0; CP0 to CP1;
see Figure8
VCC = 2.0 V 50 8 - 65 - 75 - ns
VCC = 4.5 V 10 3 - 13 - 15 - ns
VCC = 6.0 V 9 2- 11 - 13 - ns hold time CP1toCP0; CP0 to CP1;
see Figure8
VCC = 2.0 V 50 17 - 65 - 75 - ns
VCC = 4.5 V 10 6 - 13 - 15 - ns
VCC = 6.0 V 9 5 - 11 - 13 - ns
trec recovery time MRto CP0 and to CP1; see Figure9
VCC = 2.0 V 5 17 - 5 - 5 - ns
VCC = 4.5 V 5 6- 5 - 5 - ns
VCC = 6.0 V 5 5- 5 - 5 - ns
fmax maximum
frequency
CP0 or CP1; see Figure9
VCC = 2.0 V 6.0 23 - 4.8 - 4.0 - MHz
VCC = 4.5 V 30 70 - 24 - 20 - MHz
VCC = 5.0 V; =15pF
-77 - - - - - MHz
VCC = 6.0 V 25 83 - 28 - 24 - MHz
CPD power
dissipation
capacitance
VI = GND to VCC;
VCC =5V; fi =1MHz
[3] -35 - - - - - pF
74HCT4017
tpd propagation
delay
CP0 to Qn; CP0 to Q5-9;
see Figure10
[1]
VCC = 4.5 V - 25 46 - 58 - 69 ns
VCC = 5.0 V; =15pF
-21 - - - - - ns
CP1 to Qn; CP1 to Q5-9;
see Figure10
VCC = 4.5 V - 25 50 - 63 - 75 ns
VCC = 5.0 V; =15pF
-21 - - - - - ns
tPHL HIGH to LOW
propagation
delay
MR to Q[1:9];
see Figure10
VCC = 4.5 V - 22 46 - 58 - 69 ns
tPLH LOW to HIGH
propagation
delay
MR to Q5-9, Q0;
see Figure10
VCC = 4.5 V - 20 46 - 58 - 69 ns
Table 7. Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure11.
NXP Semiconductors 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W): =CPD VCC2fi N+ (CL VCC2 fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs. transition time see Figure10 [2]
VCC = 4.5 V - 7 15 - 19 - 22 ns pulse width CP0 and CP1 (HIGH or
LOW); see Figure9
VCC = 4.5 V 16 7 - 20 - 24 - ns
MR (HIGH); see Figure9
VCC = 4.5 V 16 4 - 20 - 24 - ns
tsu set-up time CP1toCP0; CP0 to CP1;
see Figure8
VCC = 4.5 V 10 3 - 13 - 15 - ns hold time CP1toCP0; CP0 to CP1;
see Figure8
VCC = 4.5 V 10 6 - 13 - 15 - ns
trec recovery time MRto CP0 and to CP1; see Figure9
VCC = 4.5 V 5 5- 5 - 5 - ns
fmax maximum
frequency
CP0 or CP1; see Figure9
VCC = 4.5 V 30 61 - 24 - 20 - MHz
VCC = 5.0 V; =15pF
-67 - - - - - MHz
CPD power
dissipation
capacitance
VI = GND to VCC 1.5V;
VCC =5V; fi =1MHz
[3] -36 - - - - - pF
Table 7. Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure11.
NXP Semiconductors 74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
11. Waveforms
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