74HC40105D ,4-bit x 16-word FIFO registerFeatures and benefits Independent asynchronous inputs and outputs Expandable in either direction ..
74HC40105D ,4-bit x 16-word FIFO registerFEATURES different shifting rates. This feature makes it particularlyuseful as a buffer between asy ..
74HC40105DB ,4-bit x 16-word FIFO registerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC40105N ,4-bit x 16-word FIFO registerGENERAL DESCRIPTIONhave buffered outputs. Since all empty locations “bubble”automatically to the in ..
74HC40105PW ,4-bit x 16-word FIFO registerGENERAL DESCRIPTIONhave buffered outputs. Since all empty locations “bubble”automatically to the in ..
74HC4015D ,Dual 4-bit serial-in/parallel-out shift registerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74LVT16244MTD ,Low Voltage 16-Bit Buffer/Line Driver with 3-STATE OutputsFunctional DescriptionThe LVT16244 and LVTH16244 contain sixteen non-invert-ing buffers with 3-STAT ..
74LVT16244MTDX ,Low Voltage 16-Bit Buffer/Line Driver with 3-STATE OutputsFunctional DescriptionThe LVT16244 and LVTH16244 contain sixteen non-invert-ing buffers with 3-STAT ..
74LVT16245 ,Low Voltage 16-Bit Transceiver with 3-STATE OutputsFeaturesThe LVT16245 and LVTH16245 contain sixteen non-invert-
74HC40105D-74HCT40105N
4-bit x 16-word FIFO register
1. General descriptionThe 74HC40105; 74HCT40105 is a first-in/first-out (FIFO) "elastic" storage register that
can store 16 4-bit words. It can handle input and output data at different shifting rates.
This feature makes it particularly useful as a buffer between asynchronous systems. Each
word position in the register is clocked by a control flip-flop, which stores a marker bit. A
logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in
that position. The control flip-flop detects the state of the preceding flip-flop and
communicates its own status to the succeeding flip-flop. When a control flip-flop is in the
logic 0 state and sees a logic 1 in the preceding flip-flop, it generates a clock pulse. The
clock pulse transfers data from the preceding four data latches into its own four data
latches and resets the preceding flip-flop to logic 0. The first and last control flip-flops have
buffered outputs. All empty locations "bubble" automatically to the input end, and all valid
data ripples through to the output end. As a result, the status of the first control flip-flop
(data-in ready output - DIR) indicates if the FIFO is full. The status of the last flip-flop
(data-out ready output - DOR) indicates whether the FIFO contains data. As the earliest
data is removed from the bottom of the data stack (output end), all data entered later will
automatically ripple toward the output. Inputs include clamp diodes that enable the use of
current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits Independent asynchronous inputs and outputs Expandable in either direction Reset capability Status indicators on inputs and outputs 3-state outputs Input levels: For 74HC40105: CMOS level For 74HCT40105: TTL level 3-state outputs Complies with JEDEC standard JESD7A ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125C
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
Rev. 3 — 25 September 2013 Product data sheet
NXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO register
3. Ordering information
4. Functional diagram
Table 1. Ordering information74HC40105N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT40105N
74HC40105D 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HCT40105D
74HC40105DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HCT40105DB
74HC40105PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
NXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO registerNXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO register
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 output enable input (active LOW)
DIR 2 data-in-ready output 3 shift-in input (LOW-to-HIGH, edge triggered)
D0 to D3 4, 5, 6, 7 parallel data input
GND 8 ground (0V) 9 asynchronous master-reset input (active HIGH)
Q0 to Q3 13, 12, 11, 10 data output
DOR 14 data-out-ready output 15 shift-out input (HIGH-to-LOW, edge triggered)
VCC 16 supply voltage
NXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO register
6. Functional description
6.1 Inputs and outputs
6.1.1 Data inputs (D0 to D3)As there is no weighting of the inputs, any input can be assigned as the MSB. The size of
the FIFO memory can be reduced from the 4 x 16 configuration. For example, it can be
reduced to 3 x 16, down to 1 x 16, by tying unused data input pins to VCC or GND.
6.1.2 Data outputs (Q0 to Q3)As there is no weighting of the outputs, any output can be assigned as the MSB. The size
of the FIFO memory can be reduced from the 4 x 16 configuration as described for data
inputs. In a reduced format, the unused data outputs pins must be left open circuit.
6.1.3 Master-reset (MR)When MR is HIGH, the control functions within the FIFO are cleared, and date content is
declared invalid. The data-in ready (DIR) flag is set HIGH and the data-out-ready (DOR)
flag is set LOW. The output stage remains in the state of the last word that was shifted out,
or in the random state existing at power-up.
6.1.4 Status flag outputs (DIR, DOR)Two status flags, data-in-ready (DIR) and data-out-ready (DOR), indicate the status of the
FIFO: DIR = HIGH indicates that the input stage is empty and ready to accept valid data; DIR = LOW indicates that the FIFO is full or that a previous shift-in operation is not
complete (busy); DOR = HIGH assures valid data is present at the outputs Q0 to Q3 (does not indicate
that new data is awaiting transfer into the output stage); DOR = LOW indicates that the output stage is busy or there is no valid data.
6.1.5 Shift-in control (SI)Data is loaded into the input stage on a LOW-to-HIGH transition of SI. It also triggers an
automatic data transfer process (ripple through). If SI is held HIGH during reset, data is
loaded at the falling edge of the MR signal.
6.1.6 Shift-out control (SO)A HIGH-to-LOW transition of SO causes the DOR flags to go LOW. A HIGH-to-LOW
transition of SO causes upstream data to move into the output stage, and empty locations
to move towards the input stage (bubble-up).
6.1.7 Output enable (OE)The outputs Q0 to Q3 are enabled when OE = LOW. When OE = HIGH the outputs are in
the high impedance OFF-state.
NXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO register
6.2 Data inputFollowing power-up, the master-reset (MR) input is pulsed HIGH to clear the FIFO
memory (see Figure 7). The data-in-ready flag (DIR = HIGH) indicates that the FIFO input
stage is empty and ready to receive data. When DIR is valid (HIGH), data present at D0 to
D3 can be shifted-in using the SI control input. With SI = HIGH, data is shifted into the
input stage. DIR going LOW provides a busy indication. The data remains at the first
location in the FIFO until DIR is set to HIGH and data moves through the FIFO to the
output stage, or to the last empty location. If the FIFO is not full after the SI pulse, DIR
again becomes valid (HIGH) to indicate that space is available in the FIFO. The DIR flag
remains LOW if the FIFO is full (see Figure 8). To complete the shift-in process, the SI use
must be made LOW. With the FIFO full, SI can be held HIGH until a shift-out (SO) pulse
occurs. Then, following a shift-out of data, an empty location appears at the FIFO input
and DIR goes HIGH to allow the next data to be shifted-in. This data remains at the first
FIFO location until SI goes LOW (see Figure 9).
6.3 Data transferAfter data has been transferred from the input stage of the FIFO following SI = LOW, data
moves through the FIFO asynchronously and is stacked at the output end of the register.
Empty locations appear at the input end of the FIFO as data moves through the device.
6.4 Data outputThe data-out-ready flag (DOR = HIGH) indicates that there is valid data at the output (Q0
to Q3). The initial master-reset at power-on (MR = HIGH) sets DOR to LOW (see
Figure 7). After MR = LOW, data shifted into the FIFO moves through to the output stage
causing DOR to go HIGH. As the DOR flag goes HIGH, data can be shifted-out using the
SO = HIGH, data in the output stage is shifted out. DOR going LOW provides a busy
indication. When SO is made LOW, data moves through the FIFO to fill the output stage
and an empty location appears at the input stage. When the output stage is filled DOR
goes HIGH, but if the last of the valid data has been shifted-out leaving the FIFO empty
the DOR flag remains LOW (see Figure 11). With the FIFO empty, the last word that was
shifted-out is latched at the output Q0 to Q3.
With the FIFO empty, the SO input can be held HIGH until the SI control input is used.
Following an SI pulse, data moves through the FIFO to the output stage, resulting in the
DOR flag pulsing HIGH and a shift-out of data occurring. The SO control must be made
LOW before additional data can be shifted-out (see Figure 14).
6.5 High-speed burst modeAssuming the shift-in/shift-out pulses are not applied until the respective status flags are
valid, it follows that the status flags determine the shift-in/shift-out rates. However, without
the status flags, a high-speed burst can be implemented. In this mode, pulse widths
determine the burst-in/ burst-out rates of the shift-in/shift-out inputs. Burst rates of 35 MHz
can be obtained. Shift pulses can be applied without regard to the status flags but shift-in
pulses that would overflow the storage capacity of the FIFO are not allowed (see
Figure 12 and Figure 13).
NXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO register
6.6 Expanded formatWith the addition of a logic gate, the FIFO is easily expanded to increase word length (see
Figure 19). The basic operation and timing are identical to a single FIFO, except for an
additional gate delay on the flag outputs. If during application, the following occurs:
SI is held HIGH when the FIFO is empty, some additional logic is required to produce
a composite DIR pulse (see Figure 9 and Figure 20).
Due to the part-to-part spread of the ripple through time, the SI signals of FIFOA and
FIFOB do not always coincide. As a result, the AND-gate does not produce a composite
flag signal. The solution is given in Figure 20. The “40105” is easily cascaded to increase
the word capacity and no external components are needed. In the cascaded
configuration, the FIFOs perform all necessary communications and timing. The minimum
flag pulse widths and the flag delays determine the intercommunication speed. The data
rate of cascaded devices is typically 25 MHz. Word-capacity can be expanded to and
beyond 32-words x 4-bits (see Figure 21).
7. Limiting values[1] For DIP16 packages: above 70 C the value of Ptot derates linearly with 12 mW/K.
[2] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
[3] For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
Table 3. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V - 20 mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V - 20 mA output current VO = 0.5 V to (VCC +0.5V) - 25 mA
ICC supply current - +50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation DIP16 package [1]- 750 mW
SO16 package [2]- 500 mW
(T)SSOP16 package [3]- 500 mW
NXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO register
8. Recommended operating conditions
9. Static characteristics
Table 4. Recommended operating conditions Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 5. Static characteristicsAt recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC40105VIH HIGH-level
input voltage
VCC= 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC= 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC= 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC= 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC= 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC= 6.0V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage =VIHorVIL= 20 A; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= 20 A; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= 20 A; VCC= 6.0V 5.9 6.0 - 5.9 - 5.9 - V= 4mA; VCC= 4.5V 3.98 4.32 - 3.84 - 3.7 - V= 5.2 mA; VCC= 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage =VIHorVIL =20 A; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V =20 A; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V =20 A; VCC= 6.0V - 0 0.1 - 0.1 - 0.1 V= 4 mA; VCC= 4.5V - 0.15 0.26 - 0.33 - 0.4 V= 5.2 mA; VCC= 6.0V - 0.15 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =6.0V 0.1 - 1.0 - 1.0 A
IOZ OFF-state
output current =VIHor VIL; =VCCor GND;
VCC =6.0V 0.5 - 5.0 - 10.0 A
NXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO registerICC supply current VI =VCCor GND; IO =0A;
VCC =6.0V 8 - 80 - 160 A input
capacitance
-3.5 - pF
74HCT40105VIH HIGH-level
input voltage
VCC= 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC= 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage =VIHor VIL; VCC =4.5V= 20A 4.4 4.5 - 4.4 - 4.4 - V=4 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage =VIHor VIL; VCC =4.5V =20A - 0 0.1 - 0.1 - 0.1 V=4 mA - 0.15 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =5.5V 0.1 - 1.0 - 1.0 A
IOZ OFF-state
output current =VIHor VIL; VCC =5.5V; =VCC or GND per input
pin; other inputs at VCC or
GND; IO =0A 0.5 - 5.0 - 10 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =5.5V 8 - 80 - 160 A
ICC additional
supply current =VCC 2.1V;
other inputs at VCCor GND;
VCC= 4.5Vto 5.5V; =0A
per input pin; Dn inputs - 30 108 - 135 - 147 A
per input pin; OE input - 75 270 - 338 - 368 A
per input pin; SI input - 40 144 - 180 - 196 A
per input pin; MR input - 150 540 - 675 - 735 A
per input pin; SO input - 40 144 - 180 - 196 A input
capacitance
-3.5 - pF
Table 5. Static characteristics …continuedAt recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO register
10. Dynamic characteristicsTable 6. Dynamic characteristicsVoltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 18.
74HC40105tpd propagation
delay
MR to DIR or DOR; see
Figure7
[1]
VCC = 2.0 V - 52 175 - 220 - 265 ns
VCC = 4.5 V - 19 35 - 44 - 53 ns
VCC =5V; CL =15pF - 16 - - - - - ns
VCC = 6.0 V - 15 30 - 37 - 45 ns
SO to Qn; see Figure10 [1]
VCC = 2.0 V - 116 400 - 500 - 600 ns
VCC = 4.5 V - 42 80 - 100 - 120 ns
VCC =5V; CL =15pF - 37 - - - - - ns
VCC = 6.0 V - 34 68 - 85 - 102 ns
tPHL HIGH to
LOW
propagation
delay
SI to DIR; see Figure8 [1]
VCC = 2.0 V - 52 210 - 265 - 315 ns
VCC = 4.5 V - 19 42 - 53 - 63 ns
VCC =5V; CL =15pF - 16 - - - - - ns
VCC = 6.0 V - 15 36 - 45 - 54 ns
SO to DOR; see
Figure11
[1]
VCC = 2.0 V - 55 210 - 265 - 315 ns
VCC = 4.5 V - 20 42 - 53 - 63 ns
VCC =5V; CL =15pF - 17 - - - - - ns
VCC = 6.0 V - 16 36 - 45 - 54 ns
tPLH LOW to
HIGH
propagation
delay
SI to DOR; see Figure14 [1][5]
VCC = 2.0 V - 564 2000 - 2500 - 3000 ns
VCC = 4.5 V - 205 400 - 500 - 600 ns
VCC = 6.0 V - 165 340 - 425 - 510 ns
SO to DIR; see Figure9 [1][6]
VCC = 2.0 V - 701 2500 - 3125 - 3750 ns
VCC = 4.5 V - 255 500 - 625 - 750 ns
VCC = 6.0 V - 204 425 - 532 - 638 ns
ten enable time OE to Qn; see Figure16 [2]
VCC = 2.0 V - 41 150 - 190 - 225 ns
VCC = 4.5 V - 15 30 - 38 - 45 ns
VCC = 6.0 V - 12 26 - 33 - 38 ns
NXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO registertdis disable time OE to Qn; see Figure16 [3]
VCC = 2.0 V - 41 140 - 175 - 210 ns
VCC = 4.5 V - 15 28 - 35 - 42 ns
VCC = 6.0 V - 12 24 - 30 - 36 ns transition
time
Qn; see Figure10 [4]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns pulse width SI HIGH or LOW;
see Figure8
VCC = 2.0 V 80 19 - 100 - 120 - ns
VCC = 4.5 V 16 7 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
SO HIGH or LOW;
see Figure11
VCC = 2.0 V 120 39 - 150 - 180 - ns
VCC = 4.5 V 24 14 - 30 - 36 - ns
VCC = 6.0 V 20 11 - 26 - 31 - ns
DIR HIGH; see Figure9
VCC = 2.0 V 12 58 180 10 225 10 270 ns
VCC = 4.5 V 6 21 36 5 45 5 54 ns
VCC = 6.0 V 5 17 31 4 38 4 46 ns
DOR LOW; see Figure14
VCC = 2.0 V 12 55 170 10 215 10 255 ns
VCC = 4.5 V 6 20 34 5 43 5 51 ns
VCC = 6.0 V 5 16 29 4 37 4 43 ns
MR HIGH; see Figure7
VCC = 2.0 V 80 22 - 100 - 120 - ns
VCC = 4.5 V 16 8 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
trec recovery
time
MR to SI; see Figure15
VCC = 2.0 V 50 14 - 65 - 75 - ns
VCC = 4.5 V 10 5 - 13 - 15 - ns
VCC = 6.0 V 9 4 - 11 - 13 - ns
tsu set-up time Dn to SI; see Figure17
VCC = 2.0 V 5 39 - 5- 5- ns
VCC = 4.5 V 5 14 - 5- 5- ns
VCC = 6.0 V 5 11 - 5- 5- ns
Table 6. Dynamic characteristics …continuedVoltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 18.
NXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO register hold time Dn to SI; see Figure17
VCC = 2.0 V 125 44 - 155 - 190 - ns
VCC = 4.5 V 25 16 - 31 - 38 - ns
VCC = 6.0 V 21 13 - 26 - 32 - ns
fmax maximum
frequency
SI, SO using flags or
burst mode; see Figure8
and Figure 11; see
Figure 12 and Figure13
VCC = 2.0 V 3.6 10 - 2.8 - 2.4 - MHz
VCC = 4.5 V 18 30 - 14 - 12 - MHz
VCC =5V; CL =15pF - 33 - - - - - MHz
VCC = 6.0 V 21 36 - 16 - 14 - MHz
SI, SO cascaded; see
Figure 8 and Figure11
VCC = 2.0 V 3.6 10 - 2.8 - 2.4 - MHz
VCC = 4.5 V 18 30 - 14 - 12 - MHz
VCC = 6.0 V 21 36 - 16 - 14 - MHz
CPD power
dissipation
capacitance =GNDto VCC [7] -134 - - - - - pF
Table 6. Dynamic characteristics …continuedVoltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 18.
NXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO register
74HCT40105tpd propagation
delay
MR to DIR or DOR; see
Figure7
[1]
VCC = 4.5 V - 18 35 - 44 - 53 ns
VCC =5V; CL =15pF - 15 - - - - - ns
SO to Qn; see Figure10 [1]
VCC = 4.5 V - 40 80 - 100 - 120 ns
VCC =5V; CL =15pF - 35 - - - - - ns
tPHL HIGH to
LOW
propagation
delay
SI to DIR; see Figure8 [1]
VCC = 4.5 V - 21 42 - 53 - 63 ns
VCC =5V; CL =15pF - 18 - - - - - ns
SO to DOR; see
Figure11
[1]
VCC = 4.5 V - 20 42 - 53 - 63 ns
VCC =5V; CL =15pF - 18 - - - - - ns
tPLH LOW to
HIGH
propagation
delay
SI to DOR; see Figure14 [1][5]
VCC = 4.5 V - 188 400 - 500 - 600 ns
SO to DIR; see Figure9 [1][6]
VCC = 4.5 V - 244 500 - 625 - 750 ns
ten enable time OE to Qn; see Figure16 [2]
VCC = 4.5 V - 18 35 - 44 - 53 ns
tdis disable time OE to Qn; see Figure16 [3]
VCC = 4.5 V - 15 30 - 38 - 45 ns transition
time
Qn; see Figure10 [4]
VCC = 4.5 V - 7 15 - 19 - 22 ns pulse width SI HIGH or LOW;
see Figure8
VCC = 4.5 V 16 6 - 20 - 24 - ns
SO HIGH or LOW;
see Figure11
VCC = 4.5 V 16 7 - 20 - 24 - ns
DIR HIGH; see Figure9
VCC = 4.5 V 6 20 34 5 43 5 51 ns
DOR LOW; see Figure14
VCC = 4.5 V 6 19 34 5 43 5 51 ns
MR HIGH; see Figure7
VCC = 4.5 V 16 7 - 20 - 24 - ns
trec recovery
time
MR to SI; see Figure15
VCC = 4.5 V 15 7 - 19 - 22 - ns
Table 6. Dynamic characteristics …continuedVoltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 18.
NXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO register[1] tpd is the same as tPLH and tPHL.
[2] ten is the same as tPZH and tPZL.
[3] tdis is the same as tPLZ and tPHZ.
[4] tt is the same as tTHL and tTLH.
[5] This is the ripple through delay.
[6] This is the bubble-up delay.
[7] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC = supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
tsu set-up time Dn to SI; see Figure17
VCC = 4.5 V 5 14 - 4- 4- ns hold time Dn to SI; see Figure17
VCC = 4.5 V 27 16 - 34 - 41 - ns
fmax maximum
frequency
SI, SO using flags or
burst mode; see Figure8
and Figure 11; see
Figure 12 and Figure13
VCC = 4.5 V - 28 - 12 - 10 - MHz
VCC =5V; CL =15pF - 31 - - - - - MHz
SI, SO cascaded; see
Figure 8 and Figure11
VCC = 4.5 V - 28 - 12 - 10 - MHz
CPD power
dissipation
capacitance =GNDto VCC 1.5 V [7] -145 - - - - - pF
Table 6. Dynamic characteristics …continuedVoltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 18.
NXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO register
11. Waveforms
11.1 Master reset applied with FIFO fullNXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO register
11.2 Shifting in sequence FIFO empty to FIFO full
Table 7. Measurement points74HC40105 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT40105 1.3V 1.3V 0.1VCC 0.9VCC
NXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO register
11.3 With FIFO full; SI held HIGH in anticipation of empty location
11.4 SO input to Qn outputs propagation delayNXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO register
11.5 Shifting out sequence; FIFO full to FIFO empty
11.6 Shift-in operation; high-speed burst modeNXP Semiconductors 74HC40105; 74HCT40105
4-bit x 16-word FIFO register
11.7 Shift-out operation; high-speed burst mode
