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74HC390N
Dual decade ripple counter
Philips Semiconductors Product specification
Dual decade ripple counter 74HC/HCT390
FEATURES Two BCD decade or bi-quinary counters One package can be configured to divide-by-2, 4, 5, 10,
20, 25, 50 or 100 Two master reset inputs to clear each decade counter
individually Output capability: standard ICC category: MSI
GENERAL DESCRIPTIONThe 74HC/HCT390 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT390 are dual 4-bit decade ripple counters
divided into four separately clocked sections. The counters
have two divide-by-2 sections and two divide-by-5
sections. These sections are normally used in a BCD
decade or bi-quinary configuration, since they share a
common master reset input (nMR). If the two master reset
inputs (1MR and 2MR) are used to simultaneously clear all
8 bits of the counter, a number of counting configurations
are possible within one package. The separate clocks
(nCP0 and nCP1 ) of each section allow ripple counter or
frequency division applications of divide-by-2, 4, 5, 10, 20,
25, 50 or 100.
Each section is triggered by the HIGH-to-LOW transition of
the clock inputs (nCP0 and nCP1 ). For BCD decade
operation, the nQ0 output is connected to the nCP1 input
of, the divide-by-5 section. For bi-quinary decade
operation, the nQ3 output is connected to the nCP0 input
and nQ0 becomes the decade output.
The master reset inputs (1MR and 2MR) are active HIGH
asynchronous inputs to each decade counter which
operates on the portion of the counter identified by the “1”
and “2” prefixes in the pin configuration. A HIGH level on
the nMR input overrides the clocks and sets the four
outputs LOW.
QUICK REFERENCE DATAGND=0 V; Tamb =25 °C; tr =tf= 6 ns
Notes CPD is used to determine the dynamic power dissipation (PD in μW): =CPD× VCC2×fi +∑ (CL× VCC2× fo) where:= input frequency in MHz= output frequency in MHz (CL× VCC2×fo)= sum of outputs= output load capacitance in pF
VCC= supply voltage in V For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC −1.5V
Philips Semiconductors Product specification
Dual decade ripple counter 74HC/HCT390
ORDERING INFORMATIONSee “74HC/HCT/HCU/HCMOS Logic Package Information”.
PIN DESCRIPTION
Philips Semiconductors Product specification
Dual decade ripple counter 74HC/HCT390
BCD COUNT SEQUENCE
FOR 1/2 THE “390”
Notes Output Q0 connected to nCP1
with counter input on nCP0.= HIGH voltage level= LOW voltage level
BI-QUINARY COUNT SEQUENCE
FOR 1/2 THE “390”
Note Output Q3 connected to nCP0
with counter input on nCP1.
Philips Semiconductors Product specification
Dual decade ripple counter 74HC/HCT390
DC CHARACTERISTICS FOR 74HCFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HCGND=0 V; tr =tf=6 ns; CL =50pF
Philips Semiconductors Product specification
Dual decade ripple counter 74HC/HCT390
DC CHARACTERISTICS FOR 74HCTFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT typesThe value of additional quiescent supply current (ΔICC) for a unit load of 1 is given in the family specifications.
To determine ΔICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCTGND=0 V; tr =tf=6 ns; CL =50pF
