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74HC377PW-74HCT377N
Octal D-type flip-flop with data enable; positive-edge trigger
1. General descriptionThe 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device
features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume
the state of their corresponding Dn inputs that meet the set-up and hold time requirements
on the LOW-to-HIGH clock (CP) transition. Input E must be stable one set-up time prior to
the LOW-to-HIGH transition for predictable operation. Inputs include clamp diodes that
enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits Common clock and master reset Eight positive edge-triggered D-type flip-flops Complies with JEDEC standard no. 7A Input levels: For 74HC377: CMOS level For 74HCT377: TTL level ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V. Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125C
3. Ordering information
74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 3 — 25 September 2013 Product data sheet
Table 1. Ordering information74HC377N 40 C to +85 C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HCT377N
74HC377D 40 C to +85 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74HCT377D
74HC377DB 40 C to +85 C SSOP20 plastic shrink small outline package; 20 leads; body width
5.3 mm
SOT339-1
74HCT377DB
74HC377PW 40 C to +85 C TSSOP20 plastic thin shrink small outline package; 20 leads; body
width 4.4 mm
SOT360-1
74HCT377PW
NXP Semiconductors 74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
4. Functional diagramNXP Semiconductors 74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
NXP Semiconductors 74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
5. Pinning information
5.1 Pinning
5.2 Pin description
6. Functional description[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Table 2. Pin description 1 data enable input (active LOW)
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 2, 5, 6, 9, 12, 15, 16, 19 flip-flop output
D0, D1, D2, D3, D4, D5, D6, D7 3, 4, 7, 8, 13, 14, 17, 18 data input
GND 10 ground (0V) 11 clock input (LOW-to-HIGH, edge triggered)
VCC 20 supply voltage
Table 3. Function table[1]load “1” lh H
load “0” llL
hold (do nothing) h X no change H X no change
NXP Semiconductors 74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
7. Limiting values[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP20 package: above 70 C the value of Ptot derates linearly with 12 mW/K.
[3] For SO20 package: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V)
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5V [1]- 20 mA
IOK output clamping current VO < 0.5 V or VO >VCC +0.5V [1]- 20 mA output current 0.5 V
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125C
DIP20 package [2]- 750 mW
SO20, SSOP20, TSSOP20 [3]- 500 mW
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 - +125 40 - +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
NXP Semiconductors 74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
9. Static characteristicsTable 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC377
VIH HIGH-level
input voltage
VCC = 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC = 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND; VCC =6.0V - - 0.1 - 1- 1 A
ICC supply current VI = VCC or GND; IO =0A;
VCC =6.0V - 8.0 - 80 - 160 A input
capacitance
-3.5 - - - - - pF
74HCT377
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = 20A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = 20 A; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA; VCC = 5.5V - 0.15 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND; VCC =5.5V - - 0.1 - 1- 1 A
NXP Semiconductors 74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
10. Dynamic characteristics
ICC supply current VI = VCC or GND; IO =0A;
VCC =5.5V - 8.0 - 80 - 160 A
ICC additional
supply current
per input pin; VI =VCC 2.1V;
other inputs at VCC or GND;
VCC= 4.5Vto 5.5V
E input - 150 540 - 675 - 735 A
CP input - 50 180 - 225 - 245 A
Dn input - 20 72 - 90 - 98 A input
capacitance
-3.5 - - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Table 7. Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure8
74HC377
tpd propagation
delay
CP to Qn; see Figure6 [1]
VCC = 2.0V - 44 160 - 200 - 240 ns
VCC = 4.5V - 16 32 - 40 - 48 ns
VCC = 5.0 V; CL =15pF - 13 - - - - - -
VCC = 6.0V - 13 27 - 34 - 41 ns transition time Qn output; see Figure6 [2]
VCC = 2.0V - 19 75 - 95 - 110 ns
VCC = 4.5V - 7 15 - 19 - 22 ns
VCC = 6.0V - 6 13 - 16 - 19 ns pulse width CP input HIGHor LOW;
see Figure6
VCC = 2.0V 80 14 - 100 - 120 - ns
VCC = 4.5V 16 5 - 20 - 24 - ns
VCC = 6.0V 14 4 - 17 - 20 - ns
tsu set-up time Dn to CP; see Figure7
VCC = 2.0V 60 14 - 75 - 90 - ns
VCC = 4.5V 12 5 - 15 - 18 - ns
VCC = 6.0V 10 4 - 13 - 15 - ns
E to CP; see Figure7
VCC = 2.0V 60 6 - 75 - 90 - ns
VCC = 4.5V 12 2 - 15 - 18 - ns
VCC = 6.0V 10 2 - 13 - 15 - ns
NXP Semiconductors 74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger hold time Dn to CP; see Figure7
VCC = 2.0V 3 8- 3 - 3 - ns
VCC = 4.5V 3 3- 3 - 3 - ns
VCC = 6.0V 3 2- 3 - 3 - ns
E to CP; see Figure7
VCC = 2.0V 4 3- 4 - 4 - ns
VCC = 4.5V 4 1- 4 - 4 - ns
VCC = 6.0V 4 1- 4 - 4 - ns
fmax maximum
frequency
CP input; see Figure6
VCC = 2.0V 6 23 - 5 - 4 - MHz
VCC = 4.5V 30 70 - 24 - 20 - MHz
VCC = 5.0 V; CL =15pF - 77 - - - - - MHz
VCC = 6.0V 35 83 - 28 - 24 - MHz
CPD power
dissipation
capacitance
per package; =GNDto VCC
[3] -20- - - - - pF
74HCT377
tpd propagation
delay
CP to Qn; see Figure6 [1]
VCC = 4.5V - 17 32 - 40 - 48 ns
VCC = 5.0 V; CL =15pF - 14 - - - - - ns transition time Qn output; see Figure6 [2]
VCC = 4.5V - 7 15 - 19 - 22 ns pulse width CP input; see Figure6
VCC = 4.5V 20 8 - 25 - 30 - ns
tsu set-up time Dn to CP; see Figure7
VCC = 4.5V 12 4 - 15 - 18 - ns
E to CP; see Figure7
VCC = 4.5V 22 12 - 28 - 33 - ns hold time Dn to CP; see Figure7
VCC = 4.5V 2 4- 2 - 2 - ns
E to CP; see Figure7
VCC = 4.5V 3 2- 3 - 3 - ns
fmax maximum
frequency
CP input; see Figure6
VCC = 4.5 V 27 48 - 22 - 18 - MHz
VCC = 5.0 V; CL =15pF - 53 - - - - - MHz
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure8
NXP Semiconductors 74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC 2 fi + (CL VCC 2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC 2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
11. Waveforms
CPD power
dissipation
capacitance
per package; =GNDto VCC 1.5 V
[3] -20- - - - - pF
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure8
NXP Semiconductors 74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
Table 8. Measurement points
74HC377 VCC 0.5VCC 0.5VCC
74HCT377 3V 1.3V 1.3V
