74HC373D-74HC373DB-74HC373N Fast Delivery |IC PHOENIX CO.,LIMITED

74HC373D ,74HC/HCT373; Octal D-type transparent latch; 3-stateLogic diagram (one latch) D0 D1 D2 D3 D4 D5 D6 D7D Q D Q D Q D Q D Q D Q D Q D QLATCH LATCH LATCH L ..
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74HC373D-74HC373DB-74HC373N
Octal D-type transparent latch; 3-state
1. General description
The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type
inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all latches.
The 74HC373; 74HCT373 consists of eight D-type transparent latches with 3-state true
outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding input changes.
When LE is LOW the latches store the information that was present at the D inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-
impedance OFF-state. Operation of the OE input does not affect the state of the latches.
The 74HC373; 74HCT373 is functionally identical to: 74HC563; 74HCT563: but inverted outputs and different pin arrangement 74HC573; 74HCT573: but different pin arrangement
2. Features and benefits 3-state non-inverting outputs for bus oriented applications Common 3-state output enable input Functionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573 ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Specified from 40 Cto+85 C and from 40 Cto+125C
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Rev. 5 — 13 December 2011 Product data sheet
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
74HC373N 40Cto +125C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HCT373N
74HC373D 40Cto +125C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74HCT373D
74HC373DB 40Cto +125C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
74HCT373DB
74HC373PW 40Cto +125C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74HCT373PW
74HC373BQ 40Cto +125C DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
SOT764-1
74HCT373BQ
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 3-state output enable input (active LOW)
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 2, 5, 6, 9, 12, 15, 16, 19 3-state latch output
D0, D1, D2, D3, D4, D5, D6, D7 3, 4, 7, 8, 13, 14, 17, 18 data input
GND 10 ground (0V) 11 latch enable input (active HIGH)
VCC 20 supply voltage
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
6. Functional description
6.1 Function table
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
7. Limiting values
[1] For DIP20 package: Ptot derates linearly with 12 mW/K above 70C.
[2] For SO20: Ptot derates linearly with 8 mW/K above 70C.
[3] For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60C.
[4] For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60C.
Table 3. Function table[1]
Enable and read register
(transparent mode) LL L H
Latch and read register L L l L L H
Latch register and disable
outputs XXX Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V - 20 mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V - 20 mA output current VO = 0.5 V to (VCC +0.5V) - 35 mA
ICC supply current - +70 mA
IGND ground current - 70 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation
DIP20 package [1]- 750 mW
SO20 package [2]- 500 mW
SSOP20 package [3] 500 mW
TSSOP20 package [3] 500 mW
DHVQFN20 package [4]- 500 mW
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics 74HC373
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Tamb =25C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 V
VCC = 4.5 V - 2.1 1.35 V
VCC = 6.0 V - 2.8 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL -- -= 20 A; VCC= 2.0V 1.9 2.0 - V= 20 A; VCC= 4.5V 4.4 4.5 - V= 20 A; VCC= 6.0V 5.9 6.0 - V
IO = 6.0 mA; VCC = 4.5 V 3.98 4.32 - V
IO = 7.8 mA; VCC = 6.0 V 5.48 5.81 - V
VOL LOW-level output voltage VI = VIH or VIL =20 A; VCC= 2.0V - 0 0.1 V =20 A; VCC= 4.5V - 0 0.1 V =20 A; VCC= 6.0V - 0 0.1 V
IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 V
IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 V input leakage current VI =VCCor GND; VCC = 6.0 V - - 0.1 A
IOZ OFF-state output current VI =VIHor VIL; VCC =6.0V; =VCC or GND 0.5 A
ICC supply current VCC = 6.0 V; IO = 0 A; =VCCor GND 8.0 A input capacitance - 3.5 - pF
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Tamb= 40 Cto+85C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL= 20 A; VCC= 2.0V 1.9 - - V= 20 A; VCC= 4.5V 4.4 - - V= 20 A; VCC= 6.0V 5.9 - - V
IO = 6.0 mA; VCC = 4.5 V 3.84 - - V
IO = 7.8 mA; VCC = 6.0 V 5.34 - - V
VOL LOW-level output voltage VI = VIH or VIL =20 A; VCC= 2.0V - - 0.1 V =20 A; VCC= 4.5V - - 0.1 V =20 A; VCC= 6.0V - - 0.1 V
IO = 6.0 mA; VCC = 4.5 V - - 0.33 V
IO = 7.8 mA; VCC = 6.0 V - - 0.33 V input leakage current VI =VCCor GND; VCC = 6.0 V - - 1.0 A
IOZ OFF-state output current VI =VIHor VIL; VCC =6.0V; =VCC or GND 5.0 A
ICC supply current VCC = 6.0 V; IO =0 A; =VCCor GND
-80 A
Tamb= 40Cto +125C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL= 20 A; VCC= 2.0V 1.9 - - V= 20 A; VCC= 4.5V 4.4 - - V= 20 A; VCC= 6.0V 5.9 - - V
IO = 6.0 mA; VCC = 4.5 V 3.7 - - V
IO = 7.8 mA; VCC = 6.0 V 5.2 - - V
Table 6. Static characteristics 74HC373 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
VOL LOW-level output voltage VI = VIH or VIL =20 A; VCC= 2.0V - - 0.1 V =20 A; VCC= 4.5V - - 0.1 V =20 A; VCC= 6.0V - - 0.1 V
IO = 6.0 mA; VCC = 4.5 V - - 0.4 V
IO = 7.8 mA; VCC = 6.0 V - - 0.4 V input leakage current VI =VCCor GND; VCC = 6.0 V - - 1.0 A
IOZ OFF-state output current VI =VIHor VIL; VCC =6.0V; =VCC or GND 10.0 A
ICC supply current VCC = 6.0 V; IO = 0 A; =VCCor GND 160 A
Table 6. Static characteristics 74HC373 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Table 7. Static characteristics 74HCT373
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb =25C
VIH HIGH-level input voltage VCC= 4.5 V to 5.5V 2.0 1.6 - V
VIL LOW-level input voltage VCC= 4.5 V to 5.5V - 1.2 0.8 V
VOH HIGH-level output voltage VI =VIHorVIL= 20 A; VCC= 4.5V 4.4 4.5 - V= 6.0 mA; VCC= 4.5V 3.98 4.32 - V
VOL LOW-level output voltage VI =VIHorVIL =20 A; VCC= 4.5V - 0.0 0.1 V =6.0 mA; VCC= 4.5V - 0.16 0.26 V input leakage current VI =VCCor GND; VCC =5.5V - - 0.1 A
IOZ OFF-state output current VI =VIHor VIL; VCC =5.5V; =VCC or GND per input pin;
other inputsat VCCor GND; IO =0 A 0.5 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =5.5V 8.0 A
ICC additional supply current VI =VCC 2.1V;
other inputsat VCCor GND;
VCC= 4.5Vto 5.5 V; IO =0A - 30 108 A - 150 540 A - 100 360 A input capacitance - 3.5 - pF
Tamb= 40 C to +85C
VIH HIGH-level input voltage VCC= 4.5 V to 5.5V 2.0 - - V
VIL LOW-level input voltage VCC= 4.5 V to 5.5V - - 0.8 V
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
VOH HIGH-level output voltage VI =VIHorVIL= 20 A; VCC= 4.5V 4.4 - - V= 6.0 A; VCC =4.5V 3.84 - - V
VOL LOW-level output voltage VI =VIHorVIL =20 A; VCC= 4.5V - - 0.1 V =6.0 mA; VCC =4.5V - - 0.33 V input leakage current VI =VCCor GND; VCC =5.5V - - 1.0 A
IOZ OFF-state output current VI =VIHor VIL; VCC =5.5V; =VCC or GND per input pin;
other inputsat VCCor GND; IO =0 A 5.0 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =5.5V 80 A
ICC additional supply current VI =VCC 2.1V;
other inputsat VCCor GND;
VCC= 4.5Vto 5.5 V; IO =0A - - 135 A - - 675 A -- 450 A
Tamb= 40 C to +125C
VIH HIGH-level input voltage VCC= 4.5 V to 5.5V 2.0 - - V
VIL LOW-level input voltage VCC= 4.5 V to 5.5V - - 0.8 V
VOH HIGH-level output voltage VI =VIHorVIL= 20 A; VCC= 4.5V 4.4 - - V= 6.0 mA; VCC= 4.5V 3.7 - - V
VOL LOW-level output voltage VI =VIHorVIL =20 A; VCC= 4.5V - - 0.1 V =6.0 mA; VCC =4.5V - - 0.4 V input leakage current VI =VCCor GND; VCC =5.5V - - 1.0 A
IOZ OFF-state output current VI =VIHor VIL; VCC =5.5V; =VCC or GND per input pin;
other inputsat VCCor GND; IO =0 A 10 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =5.5V 160 A
ICC additional supply current VI =VCC 2.1V;
other inputsat VCCor GND;
VCC= 4.5Vto 5.5 V; IO =0A - - 147 A - - 735 A -- 490 A
Table 7. Static characteristics 74HCT373 …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
10. Dynamic characteristicsTable 8. Dynamic characteristics 74HC373
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Tamb =25C
tpd propagation delay Dn to Qn; see Figure8 [1]
VCC = 2.0 V - 41 150 ns
VCC = 4.5 V - 15 30 ns
VCC =5V; CL =15pF - 12 - ns
VCC = 6.0 V - 12 26 ns
LE to Qn; see Figure9
VCC = 2.0 V - 50 175 ns
VCC = 4.5 V - 18 35 ns
VCC =5V; CL =15pF - 15 - ns
VCC = 6.0 V - 14 30 ns
ten enable time OE to Qn; see Figure10 [2]
VCC = 2.0 V - 44 150 ns
VCC = 4.5 V - 16 30 ns
VCC = 6.0 V - 13 26 ns
tdis disable time OE to Qn; see Figure10 [3]
VCC = 2.0 V - 47 150 ns
VCC = 4.5 V - 17 30 ns
VCC = 6.0 V - 14 26 ns transition time Qn; see Figure 8 and Figure9 [4]
VCC = 2.0 V - 14 60 ns
VCC = 4.5 V - 5 12 ns
VCC = 6.0 V - 4 10 ns pulse width LE HIGH; see Figure9
VCC = 2.0 V 80 17 - ns
VCC = 4.5 V 16 6 - ns
VCC = 6.0 V 14 5 - ns
tsu set-up time Dn to LE; see Figure11
VCC = 2.0 V 50 14 - ns
VCC = 4.5 V 10 5 - ns
VCC = 6.0 V 9 4 - ns hold time Dn to LE; see Figure11
VCC = 2.0 V +5 8- ns
VCC = 4.5 V +5 3- ns
VCC = 6.0 V +5 2- ns
CPD power dissipation capacitance per latch; VI =GNDto VCC [5] -45 -pF
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Tamb= 40 Cto+85C
tpd propagation delay Dn to Qn; see Figure8 [1]
VCC = 2.0 V - - 190 ns
VCC = 4.5 V - - 38 ns
VCC = 6.0 V - - 33 ns
LE to Qn; see Figure9
VCC = 2.0 V - - 220 ns
VCC = 4.5 V - - 44 ns
VCC = 6.0 V - - 37 ns
ten enable time OE to Qn; see Figure10 [2]
VCC = 2.0 V - - 190 ns
VCC = 4.5 V - - 38 ns
VCC = 6.0 V - - 33 ns
tdis disable time OE to Qn; see Figure10 [3]
VCC = 2.0 V - - 190 ns
VCC = 4.5 V - - 38 ns
VCC = 6.0 V - - 33 ns transition time Qn; see Figure 8 and Figure9 [4]
VCC = 2.0 V - - 75 ns
VCC = 4.5 V - - 15 ns
VCC = 6.0 V - - 13 ns pulse width LE HIGH; see Figure9
VCC = 2.0 V 100 - - ns
VCC = 4.5 V 20 - - ns
VCC = 6.0 V 17 - - ns
tsu set-up time Dn to LE; see Figure11
VCC = 2.0 V 65 - - ns
VCC = 4.5 V 13 - - ns
VCC = 6.0 V 11 - - ns hold time Dn to LE; see Figure11
VCC = 2.0 V 5 - - ns
VCC = 4.5 V 5 - - ns
VCC = 6.0 V 5 - - ns
Table 8. Dynamic characteristics 74HC373 …continued
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Tamb= 40Cto +125C
tpd propagation delay Dn to Qn; see Figure8 [1]
VCC = 2.0 V - - 225 ns
VCC = 4.5 V - - 45 ns
VCC = 6.0 V - - 38 ns
LE to Qn; see Figure9
VCC = 2.0 V - - 265 ns
VCC = 4.5 V - - 53 ns
VCC = 6.0 V - - 45 ns
ten enable time OE to Qn; see Figure10 [2]
VCC = 2.0 V - - 225 ns
VCC = 4.5 V - - 45 ns
VCC = 6.0 V - - 38 ns
tdis disable time OE to Qn; see Figure10 [3]
VCC = 2.0 V - - 225 ns
VCC = 4.5 V - - 45 ns
VCC = 6.0 V - - 38 ns transition time Qn; see Figure 8 and Figure9 [4]
VCC = 2.0 V - - 90 ns
VCC = 4.5 V - - 18 ns
VCC = 6.0 V - - 15 ns pulse width LE HIGH; see Figure9
VCC = 2.0 V 120 - - ns
VCC = 4.5 V 24 - - ns
VCC = 6.0 V 20 - - ns
tsu set-up time Dn to LE; see Figure11
VCC = 2.0 V 75 - - ns
VCC = 4.5 V 15 - - ns
VCC = 6.0 V 13 - - ns
Table 8. Dynamic characteristics 74HC373 …continued
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
[1] tpd is the same as tPLH and tPHL.
[2] ten is the same as tPZH and tPZL.
[3] tdis is the same as tPLZ and tPHZ.
[4] tt is the same as tTHL and tTLH.
[5] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC = supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs. hold time Dn to LE; see Figure11
VCC = 2.0 V 5 - - ns
VCC = 4.5 V 5 - - ns
VCC = 6.0 V 5 - - ns
Table 8. Dynamic characteristics 74HC373 …continued
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Table 9. Dynamic characteristics 74HCT373
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Tamb =25C
tpd propagation delay Dn to Qn; see Figure8 [1]
VCC = 4.5 V - 17 30 ns
VCC =5V; CL =15pF - 14 - ns
LE to Qn; see Figure9
VCC = 4.5 V - 16 32 ns
VCC =5V; CL =15pF - 13 - ns
ten enable time OE to Qn; see Figure10 [2]
VCC = 4.5 V - 19 32 ns
tdis disable time OE to Qn; see Figure10 [3]
VCC = 4.5 V - 18 30 ns transition time Qn; see Figure 8 and Figure9 [4]
VCC = 4.5 V - 5 12 ns pulse width LE HIGH; see Figure9
VCC = 4.5 V 16 4 - ns
tsu set-up time Dn to LE; see Figure11
VCC = 4.5 V 12 6 - ns hold time Dn to LE; see Figure11
VCC = 4.5 V 4 1- ns
CPD power dissipation capacitance per latch; =GNDto (VCC 1.5V)
[5] -41 -pF

Partno	Mfg	Dc	Qty	Available	Descript
74HC373D	NXP	N/a	25000	avai	74HC/HCT373; Octal D-type transparent latch; 3-state
74HC373DB	NXP	N/a	3	avai	74HC/HCT373; Octal D-type transparent latch; 3-state
74HC373N	TI/PHILIPS	N/a	2240	avai	Octal D-type transparent latch; 3-state