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74HC32D NXP N/a62500avaiQuad 2-input OR gate
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74HC32D -74HC32PW-74HCT32D-74HCT32PW
Quad 2-input OR gate
1. General description
The 74HC32; 74HCT32 is a quad 2-input OR gate. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V Complies with JEDEC standard JESD7A Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays Input levels: For 74HC32: CMOS level For 74HCT32: TTL level ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Specified from 40 C to +85 C and from 40 C to +125C
74HC32; 74HCT32
Quad 2-input OR gate
Rev. 5 — 4 September 2012 Product data sheet
NXP Semiconductors 74HC32; 74HCT32
Quad 2-input OR gate
3. Ordering information
4. Functional diagram
Table 1. Ordering information
74HC32N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT32N
74HC32D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HCT32D
74HC32DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT337-1
74HCT32DB
74HC32PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74HCT32PW
74HC32BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.53 0.85 mm
SOT762-1
74HCT32BQ
NXP Semiconductors 74HC32; 74HCT32
Quad 2-input OR gate
5. Pinning information
5.1 Pinning
5.2 Pin description
6. Functional description
[1] H= HIGH voltage level;= LOW voltage level;= don’t care.
Table 2. Pin description
1A to 4A 1, 4, 9, 12 data input
1B to 4B 2, 5, 10,13 data input
1Y to 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
VCC 14 supply voltage
Table 3. Function table[1]
LLL H H
HHH
NXP Semiconductors 74HC32; 74HCT32
Quad 2-input OR gate
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60C.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V [1]- 20 mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V [1]- 20 mA output current 0.5 V < VO < VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation [2]
DIP14 package - 750 mW
SO14, (T)SSOP14 and
DHVQFN14 packages 500 mW
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 - +125 40 - +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V --83 - --ns/V
NXP Semiconductors 74HC32; 74HCT32
Quad 2-input OR gate
9. Static characteristicsTable 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC32
VIH HIGH-level
input voltage
VCC = 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC = 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC =6.0V 0.1 - 1- 1 A
ICC supply current VI = VCC or GND; IO =0A;
VCC =6.0V 2.0 - 20 - 40 A input
capacitance
-3.5 - - - - - pF
74HCT32
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = 20A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = 20A - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA - 0.15 0.25 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC =5.5V 0.1 - 1- 1 A
NXP Semiconductors 74HC32; 74HCT32
Quad 2-input OR gate
10. Dynamic characteristics
ICC supply current VI = VCC or GND; IO =0A;
VCC =5.5V 2.0 - 20 - 40 A
ICC additional
supply current
per input pin; =VCC 2.1 V; IO =0A;
other inputs at VCC or GND;
VCC= 4.5Vto 5.5V - 430 - 540 - 590 A input
capacitance
-3.5 - - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Table 7. Dynamic characteristics
GND=0 V; CL=50 pF; for load circuit see Figure7.
74HC32
tpd propagation delay nA, nB to nY; see Figure6 [1]
VCC = 2.0 V - 22 90 115 135 ns
VCC = 4.5 V - 8 18 23 27 ns
VCC = 5.0 V; CL =15pF - 6 - - - ns
VCC = 6.0 V - 6 15 20 23 ns transition time see Figure6 [2]
VCC = 2.0 V - 19 75 95 110 ns
VCC = 4.5 V - 7 15 19 22 ns
VCC = 6.0 V - 6 13 16 19 ns
CPD power dissipation
capacitance
per package; VI =GNDto VCC [3] -16- - - pF
NXP Semiconductors 74HC32; 74HCT32
Quad 2-input OR gate
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W): =CPD VCC2fi N+  (CL VCC2 fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;(CL VCC2fo)= sum of outputs.
11. Waveforms
74HCT32
tpd propagation delay nA, nB to nY; see Figure6 [1]
VCC = 4.5 V - 11 24 30 36 ns
VCC = 5.0 V; CL =15pF - 9 - - - ns transition time VCC = 4.5 V; see Figure6 [2] - 7 15 19 22 ns
CPD power dissipation
capacitance
per package; =GNDto VCC 1.5V
[3] -28- - - pF
Table 7. Dynamic characteristics
GND=0 V; CL=50 pF; for load circuit see Figure7.
Table 8. Measurement points
74HC32 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT32 1.3V 1.3V 0.1VCC 0.9VCC
NXP Semiconductors 74HC32; 74HCT32
Quad 2-input OR gate
Table 9. Test data
74HC32 VCC 6.0 ns 15 pF, 50pF tPLH, tPHL
74HCT32 3.0V 6.0 ns 15 pF, 50pF tPLH, tPHL
NXP Semiconductors 74HC32; 74HCT32
Quad 2-input OR gate
12. Package outline
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