74HC30D-74HC30PW-74HCT30D-74HCT30N Fast Delivery |IC PHOENIX CO.,LIMITED

74HC30D ,74HC/HCT30; 8-input NAND gateLogic diagram74HC_HCT30 All information provided in this document is subject to legal disclaimers. ..
74HC30N ,8-input NAND gateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC30N ,8-input NAND gateFEATURES• Output capability: standard• I category: SSICC
74HC30N ,8-input NAND gateGENERAL DESCRIPTIONThe 74HC/HCT30 are high-speed Si-gate CMOS devices and are pin compatible with l ..
74HC30N ,8-input NAND gateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC30PW ,74HC/HCT30; 8-input NAND gateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74LVC652 ,Octal transceiver/register with dual enable 3-State
74LVC74A ,positive-edge trigger
74LVC74A ,positive-edge trigger
74LVC74A ,positive-edge trigger
74LVC74A ,positive-edge trigger
74LVC74ABQ ,Dual D-type flip-flop with set and reset; positive-edge trigger

74HC30D-74HC30PW-74HCT30D-74HCT30N
8-input NAND gate
1. General description
The 74HC30; 74HCT30 is an 8-input NAND gate. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits Complies with JEDEC standard JESD7A Input levels: For 74HC30: CMOS level For 74HCT30: TTL level ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Specified from 40 C to +85 C and from 40 C to +125C
3. Ordering information
74HC30; 74HCT30
8-input NAND gate
Rev. 6 — 27 December 2012 Product data sheet
Table 1. Ordering information
74HC30N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT30N
74HC30D 40 C to +125 C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74HCT30D
74HC30DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT337-1
74HCT30DB
74HC30PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74HCT30PW
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
4. Functional diagram
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 data input 2 data input 3 data input 4 data input 5 data input 6 data input
GND 7 ground (0V) 8 data output
n.c. 9 not connected
n.c. 10 not connected 11 data input 12 data input
n.c. 13 not connected
VCC 14 supply voltage
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
6. Functional description
[1] H= HIGH voltage level; L= LOW voltage level; X= don’t care.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60C.
Table 3. Function table[1] XX XXX XXH X XXX XXH
XXL XXX XXH
XXX L XX XXH
XXX XL X XXH
XXX XXL XXH
XXX XXX L XH
XXX XXX XL H
HHH HHH HHL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V [1]- 20 mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V [1]- 20 mA output current 0.5 V < VO < VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation
DIP14 package [2]- 750 mW
SO14, (T)SSOP14 packages [2]- 500 mW
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 - +125 40 - +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC30
VIH HIGH-level
input voltage
VCC = 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC = 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC =6.0V 0.1 - 1- 1 A
ICC supply current VI = VCC or GND; IO =0A;
VCC =6.0V 2.0 - 20 - 40 A
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
10. Dynamic characteristics input
capacitance
-3.5 - - - - - pF
74HCT30
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = 20A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = 20A - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC =5.5V 0.1 - 1- 1 A
ICC supply current VI = VCC or GND; IO =0A;
VCC =5.5V 2.0 - 20 - 40 A
ICC additional
supply current
per input pin; =VCC 2.4 V; IO =0A;
other inputs at VCC or GND;
VCC= 4.5Vto 5.5V 60 216 - 275 - 294 A input
capacitance
-3.5 - - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Table 7. Dynamic characteristics
GND=0 V; CL=50 pF; for load circuit see Figure6.
74HC30
tpd propagation delay A, B, C, D, E, F, G, H to Y;
see Figure5
[1]
VCC = 2.0 V - 41 130 165 195 ns
VCC = 4.5 V - 15 26 33 39 ns
VCC = 5.0 V; CL =15pF - 12 - - - ns
VCC = 6.0 V - 12 22 28 33 ns transition time see Figure5 [2]
VCC = 2.0 V - 19 75 95 110 ns
VCC = 4.5 V - 7 15 19 22 ns
VCC = 6.0 V - 6 13 16 19 ns
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W): =CPD VCC2fi N+  (CL VCC2 fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;(CL VCC2fo)= sum of outputs.
11. Waveforms
CPD power dissipation
capacitance
per package; VI =GNDto VCC [3] -15- - - pF
74HCT30
tpd propagation delay A, B, C, D, E, F, G, H to Y;
see Figure5
[1]
VCC = 4.5 V - 16 28 35 42 ns
VCC = 5.0 V; CL =15pF - 12 - - - ns transition time VCC = 4.5 V; see Figure5 [2] - 7 15 19 22 ns
CPD power dissipation
capacitance
per package; =GNDto VCC 1.5V
[3] -15- - - pF
Table 7. Dynamic characteristics …continued
GND=0 V; CL=50 pF; for load circuit see Figure6.
Table 8. Measurement points
74HC30 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT30 1.3V 1.3V 0.1VCC 0.9VCC
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
Table 9. Test data
74HC30 VCC 6.0 ns 15 pF, 50pF tPLH, tPHL
74HCT30 3.0V 6.0 ns 15 pF, 50pF tPLH, tPHL

Partno	Mfg	Dc	Qty	Available	Descript
74HC30D	NXP	N/a	20000	avai	74HC/HCT30; 8-input NAND gate
74HC30PW		N/a	12500	avai	74HC/HCT30; 8-input NAND gate
74HCT30D	NXP	N/a	13368	avai	8-input NAND gate
74HCT30N	PH	N/a	290	avai	74HC/HCT30; 8-input NAND gate