74HC2G32DC-74HC2G32DP-74HCT2G32DC-74HCT2G32DP Fast Delivery |IC PHOENIX CO.,LIMITED

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74HC2G32DC-74HC2G32DP-74HCT2G32DC-74HCT2G32DP
Dual 2-input OR gate
1. General description
The 74HC2G32; 74HCT2G32 is a dual 2-input OR gate. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits Wide supply voltage range from 2.0 Vto 6.0V Input levels: For 74HC2G32: CMOS level For 74HCT2G32: TTL level Complies with JEDEC standard no. 7A Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays Multiple package options ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
74HC2G32; 74HCT2G32
Dual 2-input OR gate
Rev. 5 — 6 January 2014 Product data sheet
Table 1. Ordering information
74HC2G32DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74HCT2G32DP
74HC2G32DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74HCT2G32DC
74HC2G32GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; terminals; body 3  2  0.5 mm
SOT996-2
74HCT2G32GD
NXP Semiconductors 74HC2G32; 74HCT2G32
Dual 2-input OR gate
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
6. Pinning information
6.1 Pinning
Table 2. Marking code
74HC2G32DP H32
74HCT2G32DP T32
74HC2G32DC H32
74HCT2G32DC T32
74HC2G32GD H32
74HCT2G32GD T32
NXP Semiconductors 74HC2G32; 74HCT2G32
Dual 2-input OR gate
6.2 Pin description
7. Functional description
[1] H= HIGH voltage level; L= LOW voltage level.
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
Table 3. Pin description
1A, 2A 1, 5 data input
1B, 2B 2, 6 data input
GND 4 ground (0 V), 2Y 7, 3 data output
VCC 8 supply voltage
Table 4. Function table[1] L H H H
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7.0 V
IIK input clamping current VI< 0.5VorVI >VCC + 0.5V [1]- 20 mA
IOK output clamping current VO< 0.5VorVO >VCC + 0.5V [1]- 20 mA output current VO = 0.5 V to (VCC +0.5V) [1] -25 mA
ICC supply current [1] -50 mA
IGND ground current [1] 50 - mA
Tstg storage temperature 65 +150 C dynamic power dissipation Tamb = 40Cto +125C [2]- 300 mW
NXP Semiconductors 74HC2G32; 74HCT2G32
Dual 2-input OR gate
9. Recommended operating conditions
10. Static characteristics
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise
and fall rate
VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 7. Static characteristics
Voltages are referenced to GND (ground = 0 V).
74HC2G32
VIH HIGH-level
input voltage
VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage = VIH or VIL = 20 A; VCC= 2.0 V 1.9 2.0 - 1.9 - 1.9 - V = 20 A; VCC= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V = 20 A; VCC= 6.0 V 5.9 6.0 - 5.9 - 5.9 - V = 4.0 mA; VCC= 4.5 V 4.18 4.32 - 4.13 - 3.7 - V = 5.2 mA; VCC= 6.0 V 5.68 5.81 - 5.63 - 5.2 - V
VOL LOW-level
output voltage = VIH or VIL = 20 A; VCC= 2.0 V - 0 0.1 - 0.1 - 0.1 V = 20 A; VCC= 4.5 V - 0 0.1 - 0.1 - 0.1 V = 20 A; VCC= 6.0 V - 0 0.1 - 0.1 - 0.1 V = 4.0 mA; VCC= 4.5 V - 0.15 0.26 - 0.33 - 0.4 V = 5.2 mA; VCC= 6.0 V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =6.0V 0.1 - 1.0 - 1.0 A
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 6.0 V - 1.0 - 10 - 20 A
NXP Semiconductors 74HC2G32; 74HCT2G32
Dual 2-input OR gate
11. Dynamic characteristics input
capacitance
-1.5 - - - - - pF
74HCT2G32
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage = VIH or VIL; VCC= 4.5 V = 20A 4.4 4.5 - 4.4 - 4.4 - V = 4.0 mA 4.18 4.32 - 4.13 - 3.7 - V
VOL LOW-level
output voltage = VIH or VIL; VCC= 4.5 V = 20A - 0 0.1 - 0.1 - 0.1 V = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =5.5V 0.1 - 1.0 - 1.0 A
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5 V - 1.0 - 10 - 20 A
ICC additional
supply current
per input;
VCC= 4.5Vto 5.5V; =VCC 2.1 V; IO =0A - 300 - 375 - 410 A input
capacitance
-1.5 - - - - - pF
Table 7. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground =0 V); for test circuit see Figure7.
74HC2G32
tpd propagation
delay
nA, nBto nY; see Figure6 [1]
VCC = 2.0 V - 24 75 - 95 - 110 ns
VCC = 4.5 V - 9.0 15 - 19 - 22 ns
VCC = 6.0 V - 7.0 13 - 16 - 20 ns transition
time
nY; see Figure6 [2]
VCC = 2.0 V - 18 75 - 95 - 125 ns
VCC = 4.5 V - 6 15 - 19 - 25 ns
VCC = 6.0 V 5 13 - 16 - 20 ns
CPD power
dissipation
capacitance
per buffer; =50pF;fi =1 MHz; =GNDto VCC
[3] -10- - - - - pF
NXP Semiconductors 74HC2G32; 74HCT2G32
Dual 2-input OR gate
[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTLH and tTHL.
[3] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of the outputs.
12. Waveforms
74HCT2G32
tpd propagation
delay
nA, nBto nY; see Figure6 [1]
VCC = 4.5 V - 13 24 - 30 - 36 ns transition
time
nY; see Figure6 [2]
VCC = 4.5 V - 6 15 - 19 - 22 ns
CPD power
dissipation
capacitance
per buffer; =50pF;fi =1 MHz; =GNDto VCC 1.5V
[3] -11- - - - - pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground =0 V); for test circuit see Figure7.
Table 9. Measurement points
74HC2G32 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT2G32 1.3 V 1.3 V 0.1VCC 0.9VCC
NXP Semiconductors 74HC2G32; 74HCT2G32
Dual 2-input OR gate
Table 10. Test data
74HC2G32 GND to VCC  6ns 50 pF 1k open
74HCT2G32 GND to 3V  6ns 50 pF 1k open

Partno	Mfg	Dc	Qty	Available	Descript
74HC2G32DC	NXP	N/a	230	avai	Dual 2-input OR gate
74HC2G32DP	NXP	N/a	423	avai	Dual 2-input OR gate
74HC2G32DP	NXP/PHILIPS	N/a	3000	avai	Dual 2-input OR gate
74HCT2G32DC	NXP/PHIL	N/a	12000	avai	Dual 2-input OR gate
74HCT2G32DP	NXP	N/a	98	avai	Dual 2-input OR gate