74HC2G08DC-74HCT2G08DP Fast Delivery |IC PHOENIX CO.,LIMITED

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74HC2G08DC-74HCT2G08DP
Dual 2-input AND gate
1. General description
The 74HC2G08; 74HCT2G08 is a dual 2-input AND gate. Inputs include clamp diodes.
This enables the use of current limiting resistors to interface inputs to voltages in excess
of VCC.
2. Features and benefits Wide supply voltage range from 2.0 Vto 6.0V Input levels: For 74HC2G08: CMOS level For 74HCT2G08: TTL level Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays Multiple package options ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
74HC2G08; 74HCT2G08
Dual 2-input AND gate
Rev. 5 — 8 October 2013 Product data sheet
Table 1. Ordering information
74HC2G08DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74HCT2G08DP
74HC2G08DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74HCT2G08DC
74HC2G08GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; terminals; body 3  2  0.5 mm
SOT996-2
74HCT2G08GD
NXP Semiconductors 74HC2G08; 74HCT2G08
Dual 2-input AND gate
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 2. Marking code
74HC2G08DP H08
74HCT2G08DP T08
74HC2G08DC H08
74HCT2G08DC T08
74HC2G08GD H08
74HCT2G08GD T08
NXP Semiconductors 74HC2G08; 74HCT2G08
Dual 2-input AND gate
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H= HIGH voltage level; L= LOW voltage level.
Table 3. Pin description
1A, 2A 1, 5 data input
1B, 2B 2, 6 data input
GND 4 ground (0 V), 2Y 7, 3 data output
VCC 8 supply voltage
Table 4. Function table[1]
LLL L L
HHH
NXP Semiconductors 74HC2G08; 74HCT2G08
Dual 2-input AND gate
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7.0 V
IIK input clamping current VI< 0.5VorVI >VCC + 0.5V [1]- 20 mA
IOK output clamping current VO< 0.5VorVO >VCC + 0.5V [1]- 20 mA output current VO = 0.5 V to (VCC +0.5V) [1] -25 mA
ICC supply current [1] -50 mA
IGND ground current [1] 50 - mA
Tstg storage temperature 65 +150 C dynamic power dissipation Tamb = 40Cto +125C [2]- 300 mW
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise
and fall rate
VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
NXP Semiconductors 74HC2G08; 74HCT2G08
Dual 2-input AND gate
10. Static characteristicsTable 7. Static characteristics
Voltages are referenced to GND (ground = 0 V).
74HC2G08
VIH HIGH-level input
voltage
VCC = 2.0 V 1.5 1.2 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - V
VIL LOW-level input
voltage
VCC = 2.0 V - 0.8 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 V
VOH HIGH-level output
voltage = VIH or VIL = 20 A; VCC= 2.0V 1.9 2.0 - 1.9 - V = 20 A; VCC= 4.5V 4.4 4.5 - 4.4 - V = 20 A; VCC= 6.0V 5.9 6.0 - 5.9 - V = 4.0 mA; VCC=4.5V 4.13 4.32 - 3.7 - V = 5.2 mA; VCC=6.0V 5.63 5.81 - 5.2 - V
VOL LOW-level output
voltage = VIH or VIL = 20 A; VCC= 2.0V - 0 0.1 - 0.1 V = 20 A; VCC= 4.5V - 0 0.1 - 0.1 V = 20 A; VCC= 6.0V - 0 0.1 - 0.1 V = 4.0 mA; VCC= 4.5V - 0.15 0.33 - 0.4 V = 5.2 mA; VCC= 6.0V - 0.16 0.33 - 0.4 V input leakage current VI =VCCor GND; VCC =6.0V - - 1.0 - 1.0 A
ICC supply current per input pin; VI =VCCor GND; =0A; VCC =6.0V 10 - 20 A input capacitance - 1.5 - - - pF
NXP Semiconductors 74HC2G08; 74HCT2G08
Dual 2-input AND gate
[1] All typical values are measured at Tamb = 25C.
11. Dynamic characteristics
74HCT2G08
VIH HIGH-level input
voltage
VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V
VIL LOW-level input
voltage
VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V
VOH HIGH-level output
voltage = VIH or VIL = 20 A; VCC= 4.5V 4.4 4.5 - 4.4 - V = 4.0 mA; VCC=4.5V 4.13 4.32 - 3.7 - V
VOL LOW-level output
voltage = VIH or VIL = 20 A; VCC= 4.5V - 0 0.1 - 0.1 V = 4.0 mA; VCC= 4.5V - 0.15 0.33 - 0.4 V input leakage current VI =VCCor GND; VCC =5.5V - - 1.0 - 1.0 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =5.5V 10 - 20 A
ICC additional supply
current
per input; VCC= 4.5Vto 5.5V; =VCC 2.1 V; IO =0A - 375 - 410 A input capacitance - 1.5 - - - pF
Table 7. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground =0 V); for test circuit see Figure7.
74HC2G08
tpd propagation delay nA and nB to nY; see Figure6 [2]
VCC = 2.0 V - 26 95 - 110 ns
VCC = 4.5 V - 9 19 - 22 ns
VCC = 5.0 V; CL = 15 pF - 9 - - - ns
VCC = 6.0 V - 8 16 - 20 ns transition time see Figure6 [3]
VCC = 2.0 V - 20 95 - 125 ns
VCC = 4.5 V - 7 19 - 25 ns
VCC = 6.0 V - 6 16 - 20 ns
CPD power dissipation
capacitance =GNDto VCC [4] -10- - - pF
NXP Semiconductors 74HC2G08; 74HCT2G08
Dual 2-input AND gate
[1] All typical values are measured at Tamb = 25C.
[2] tpd is the same as tPLH and tPHL.
[3] tt is the same as tTLH and tTHL.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC 2  fi  N + (CL  VCC 2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC 2  fo) = sum of outputs.
12. Waveforms
74HCT2G08
tpd propagation delay nA and nB to nY; see Figure6 [2]
VCC = 4.5 V - 14 30 - 36 ns
VCC = 5.0 V; CL = 15 pF - 14 - - - ns transition time VCC = 4.5 V; see Figure6 [3] -7 19 - 22 ns
CPD power dissipation
capacitance =GNDto VCC 1.5V [4] -10- - - pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground =0 V); for test circuit see Figure7.
Table 9. Measurement points
74HC2G08 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT2G08 1.3 V 1.3 V 0.1VCC 0.9VCC
NXP Semiconductors 74HC2G08; 74HCT2G08
Dual 2-input AND gate
Table 10. Test data
74HC2G08 GND to VCC  6ns 15 pF, 50 pF 1k open
74HCT2G08 GND to 3V  6ns 15 pF, 50 pF 1k open

Partno	Mfg	Dc	Qty	Available	Descript
74HC2G08DC	NXP/PHIL	N/a	12000	avai	Dual 2-input AND gate
74HCT2G08DP	NXP	N/a	9000	avai	Dual 2-input AND gate