74HC240PW-74HCT240PW Fast Delivery |IC PHOENIX CO.,LIMITED

74HC240PW ,Octal buffer/line driver; 3-state; invertingGeneral descriptionThe 74HC240; 74HCT240 is a high-speed Si-gate CMOS device and is pin compatiblew ..
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74HC240PW-74HCT240PW
Octal buffer/line driver; 3-state; inverting
General descriptionThe 74HC240; 74HCT240 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL).
The 74HC240; 74HCT240 is a dual octal inverting buffer/line driver with 3-state outputs.
The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on
nOE causes the outputs to assume a high impedance OFF-state.
The 74HC240; 74HCT240 is similar to the 74HC244; 74HCT244 but has inverting
outputs. Features Inverting 3-state outputs Multiple package options Complies with JEDEC standard no. 7 A ESD protection: HBM JESD22-A114-D exceeds 2000V MM JESD22-A115-A exceeds 200V Speciﬁed from −40 °Cto+85 °C and from −40°Cto +125°C Ordering information
74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting
Rev. 03 — 2 August 2007 Product data sheet
Table 1. Ordering information
74HC240
74HC240N −40 °C to +125°C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HC240D −40 °C to +125°C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74HC240DB −40 °C to +125°C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
74HC240PW −40 °C to +125°C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74HC240BQ −40 °C to +125°C DHVQFN20 plastic dual-in-line compatible thermal enhanced
very thin quadﬂat package;no leads;20 terminals;
body 2.5× 4.5× 0.85 mm
SOT764-1
74HCT240
74HCT240N −40 °C to +125°C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
NXP Semiconductors 74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting Functional diagram
74HCT240D −40 °C to +125°C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74HCT240DB −40 °C to +125°C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
74HCT240PW −40 °C to +125°C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74HCT240BQ −40 °C to +125°C DHVQFN20 plastic dual-in-line compatible thermal enhanced
very thin quadﬂat package;no leads;20 terminals;
body 2.5× 4.5× 0.85 mm
SOT764-1
Table 1. Ordering information …continued
NXP Semiconductors 74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description
1OE 1 output enable input (active LOW)
1A0 2 data input
2Y0 3 bus output
1A1 4 data input
2Y1 5 bus output
1A2 6 data input
2Y2 7 bus output
1A3 8 data input
2Y3 9 bus output
GND 10 ground (0V)
2A3 11 data input
1Y3 12 bus output
2A2 13 data input
1Y2 14 bus output
2A1 15 data input
1Y1 16 bus output
NXP Semiconductors 74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting Functional description
[1]H= HIGH voltage level;= LOW voltage level;= don’t care;= high-impedance OFF-state. Limiting values
[1] For DIP20 packages: above 70 °C, Ptot derates linearly with 12 mW/K.
For SO20 packages: above 70 °C, Ptot derates linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 °C, Ptot derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C, Ptot derates linearly with 4.5 mW/K.
2A0 17 data input
1Y0 18 bus output
2OE 19 output enable input (active LOW)
VCC 20 supply voltage
Table 2. Pin description …continued
Table 3. Function table[1]
LLH L Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage −0.5 +7 V
IIK input clamping current VI < −0.5 V or VI >VCC+ 0.5 V - ±20 mA
IOK output clamping current VO< −0.5 V or VO >VCC+ 0.5V - ±20 mA output current −0.5 V < VO < VCC+ 0.5V - ±35 mA
ICC supply current - 70 mA
IGND ground current −70 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation [1]
DIP20 package - 750 mW
SO20, SSOP20, TSSOP20
and DHVQFN20 packages 500 mW
NXP Semiconductors 74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting Recommended operating conditions Static characteristics
Table 5. Recommended operating conditions
74HC240
VCC supply voltage 2.0 5.0 6.0 V input voltage 0 - VCC V output voltage 0 - VCC V
Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 ns/V
VCC = 4.5 V - 1.67 139 ns/V
VCC = 6.0 V - - 83 ns/V
Tamb ambient temperature −40 - +125 °C
74HCT240
VCC supply voltage 4.5 5.0 5.5 V input voltage 0 - VCC V output voltage 0 - VCC V
Δt/ΔV input transition rise and fall rate VCC = 4.5 V - 1.67 139 ns/V
Tamb ambient temperature −40 - +125 °C
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC240
VIH HIGH-level
input voltage
VCC= 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC= 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC= 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC= 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC= 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC= 6.0V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage =VIHorVIL= −20 μA; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= −20 μA; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= −20 μA; VCC= 6.0V 5.9 6.0 - 5.9 - 5.9 - V= −6.0 mA; VCC= 4.5V 3.98 4.32 - 3.84 - 3.7 - V= −7.8 mA; VCC= 6.0V 5.48 5.81 - 5.34 - 5.2 - V
NXP Semiconductors 74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting
VOL LOW-level
output voltage =VIHorVIL =20 μA; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V =20 μA; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V =20 μA; VCC= 6.0V - 0 0.1 - 0.1 - 0.1 V= 6.0 mA; VCC= 4.5V - 0.15 0.26 - 0.33 - 0.4 V= 7.8 mA; VCC= 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC= 6.0V ±0.1 - ±1.0 - ±1.0 μA
IOZ OFF-state
output current
per input pin;VI =VIHor VIL; =VCC or GND;
other inputsat VCCor GND;
VCC= 6.0 V; IO =0A ±0.5 - ±5.0 - ±10 μA
ICC supply current VI =VCCor GND; IO =0A;
VCC= 6.0V - 8.0 - 80 - 160 μA input
capacitance 3.5 - - - - - pF
74HCT240
VIH HIGH-level
input voltage
VCC= 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC= 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage =VIHor VIL; VCC= 4.5V= −20μA 4.4 4.5 - 4.4 - 4.4 - V=−6 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage =VIHor VIL; VCC= 4.5V =20μA - 0 0.1 - 0.1 - 0.1 V= 6.0 mA - 0.16 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC= 5.5V ±0.1 - ±1.0 - ±1.0 μA
IOZ OFF-state
output current
per input pin;VI =VIHor VIL; =VCC or GND;
other inputsat VCCor GND;
VCC= 5.5 V; IO =0A ±0.5 - ±5.0 - ±10 μA
ICC supply current VI =VCCor GND;
VCC= 5.5 V; IO =0A - 8.0 - 80 - 160 μA
ΔICC additional
supply current
per input pin; =VCC− 2.1V;
other inputsat VCCor GND;
VCC= 4.5Vto 5.5V; =0A
nAn or inputs - 150 540 - 675 - 735 μA
nOE input - 70 252 - 315 - 343 μA input
capacitance 3.5 - - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND=0 V; for load circuit see Figure8.
74HC240
tpd propagation delay nAn to nYn;
see Figure6
[1]
VCC = 2.0 V - 30 100 125 150 ns
VCC = 4.5 V - 11 20 25 30 ns
VCC = 5.0 V; CL =15pF - 9 - - - ns
VCC = 6.0 V - 9 17 21 26 ns
ten enable time nOE to nYn; see Figure7 [2]
VCC = 2.0 V - 39 150 190 225 ns
VCC = 4.5 V - 14 30 38 45 ns
VCC = 6.0 V - 11 26 33 38 ns
tdis disable time nOE to nYn or see Figure7 [3]
VCC = 2.0 V - 41 150 190 225 ns
VCC = 4.5 V - 15 30 38 45 ns
VCC = 6.0 V - 12 26 33 38 ns transition time see Figure6 [4]
VCC = 2.0 V - 14 60 75 90 ns
VCC = 4.5 V - 5 12 15 18 ns
VCC = 6.0 V - 4 10 13 15 ns
CPD power dissipation
capacitance
per transceiver;= GNDto VCC
[5] -30- - - pF
NXP Semiconductors 74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting
[1] tpd is the same as tPHL and tPLH.
[2] ten is the same as tPZH and tPZL.
[3] tdis is the same as tPHZ and tPLZ.
[4] tt is the same as tTHL and tTLH.
[5] CPDis used to determine the dynamic power dissipation (PD in μW): =CPD× VCC2×fi× N+ ∑ (CL× VCC2× fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;(CL× VCC2×fo)= sum of outputs.
11. Waveforms
74HCT240
tpd propagation delay nAn to nYn;
see Figure6
[1]
VCC = 4.5 V - 11 20 25 30 ns
VCC = 5.0 V; CL =15pF - 9 - - - ns
ten enable time nOE to nYn; VCC= 4.5 V; see
Figure7
[2] -13 3038 45 ns
tdis disable time nOE to nYn; VCC= 4.5 V; see
Figure7
[3] -13 2531 38 ns transition time VCC = 4.5 V; see Figure6 [4] - 5 12 15 18 ns
CPD power dissipation
capacitance
per transceiver;= GNDto VCC− 1.5V
[5] -30- - - pF
Table 7. Dynamic characteristics …continued
GND=0 V; for load circuit see Figure8.
NXP Semiconductors 74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting
Table 8. Measurement points
74HC240 0.5 × VCC 0.5 × VCC 0.1 × VCC 0.9 × VCC
74HCT240 1.3V 1.3V 0.1 × VCC 0.9 × VCC

Partno	Mfg	Dc	Qty	Available	Descript
74HC240PW	NXP	N/a	2500	avai	Octal buffer/line driver; 3-state; inverting
74HCT240PW	NXP	N/a	10	avai	Octal buffer/line driver; 3-state; inverting