74HC21D-74HC21DB-74HC21N Fast Delivery |IC PHOENIX CO.,LIMITED

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74HC21D-74HC21DB-74HC21N
Dual 4-input AND gate
1. General description
The 74HC21 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL).
The 74HC21 provide the 4-input AND function.
2. Features and benefits Low-power dissipation Complies with JEDEC standard no.7A ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125 C.
3. Ordering information
74HC21
Dual 4-input AND gate
Rev. 6 — 8 February 2013 Product data sheet
Table 1. Ordering information
74HC21N 40 C to +125C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC21D 40 C to +125C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74HC21DB 40 C to +125C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74HC21PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
NXP Semiconductors 74HC21
Dual 4-input AND gate
4. Functional diagram
5. Pinning information
5.1 Pinning
NXP Semiconductors 74HC21
Dual 4-input AND gate
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60C.
Table 2. Pin description
1A, 1B, 1C, 1D 1, 2, 4, 5 data input
n.c. 3, 11 not connected 6 data output
GND 7 ground (0V) 8 data output
2A, 2B, 2C, 2D 9, 10, 12, 13 data input
VCC 14 supply voltage
Table 3. Function table[1] XXXL XXL
XXL XL
XXXL L
HHHHH
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V [1]- 20 mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V [1]- 20 mA output current 0.5 V < VO < VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation [2]
DIP14 package - 750 mW
SO14 and (T)SSOP14
packages 500 mW
NXP Semiconductors 74HC21
Dual 4-input AND gate
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 V input voltage 0 - VCC V output voltage 0 - VCC V
t/V input transition rise and fall
rate
VCC = 2.0 V - - 625 ns/V
VCC = 4.5 V - 1.67 139 ns/V
VCC = 6.0 V - - 83 ns/V
Tamb ambient temperature 40 - +125 C
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
VIH HIGH-level
input voltage
VCC = 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC = 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC =6.0V 0.1 - 1- 1 A
ICC supply current VI = VCC or GND; IO =0A;
VCC =6.0V 2.0 - 20 - 40 A input
capacitance
-3.5 - - - - - pF
NXP Semiconductors 74HC21
Dual 4-input AND gate
10. Dynamic characteristics
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W): =CPD VCC2fi N+  (CL VCC2 fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;(CL VCC2fo)= sum of outputs.
Table 7. Dynamic characteristics
GND=0 V; test circuit see Figure8.
tpd propagation
delay
nA, nB, nC or nD to nY;
see Figure7
[1]
VCC = 2.0 V - 33 110 - 140 - 165 ns
VCC = 4.5 V - 12 22 - 28 - 33 ns
VCC = 6.0 V - 10 19 - 24 - 28 ns
VCC =5.0 V; CL=15pF - 10 - ---- ns transition time nY output; see Figure7 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
CPD power
dissipation
capacitance= GND to VCC [3] - 15 - ---- pF
NXP Semiconductors 74HC21
Dual 4-input AND gate
11. Waveforms
Table 8. Measurement points
74HC21 0.5VCC 0.5VCC 0.1VCC 0.9VCC
NXP Semiconductors 74HC21
Dual 4-input AND gate
Table 9. Test data
74HC21 VCC 6.0 ns 15 pF, 50pF tPLH, tPHL
NXP Semiconductors 74HC21
Dual 4-input AND gate
12. Package outline

Partno	Mfg	Dc	Qty	Available	Descript
74HC21D	NXP	N/a	38850	avai	Dual 4-input AND gate
74HC21DB	PH	N/a	102	avai	Dual 4-input AND gate
74HC21N	TI	N/a	20	avai	Dual 4-input AND gate