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74HC193D
74HC/HCT193; Presettable synchronous 4-bit binary up/down counter
1. General descriptionThe 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate
up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state
synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is
pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while
CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at
any time to guarantee predictable behaviour. The device can be cleared at any time by the
asynchronous master reset input (MR); it may also be loaded in parallel by activating the
asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count
down (TCD) outputs are normally HIGH. When the circuit has reached the maximum
count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW.
TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise,
the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW.
The terminal count outputs can be used as the clock input signals to the next higher order
circuit in a multistage counter, since they duplicate the clock waveforms. Multistage
counters will not be fully synchronous, since there is a slight delay time difference added
for each stage that is added. The counter may be preset by the asynchronous parallel
load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is
loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the
conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on
the master reset (MR) input will disable the parallel load gates, override both clock inputs
and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a
reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted
as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits Input levels: For 74HC193: CMOS level For 74HCT193: TTL level Synchronous reversible 4-bit binary counting Asynchronous parallel load Asynchronous reset Expandable without external logic Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V.
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Rev. 4 — 24 June 2013 Product data sheet
NXP Semiconductors 74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter Multiple package options Specified from 40 C to +85 C and 40 C to +125 C.
3. Ordering information
4. Functional diagram
Table 1. Ordering information74HC193D 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HC193DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HC193N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HC193PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT193D 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HCT193DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HCT193N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT193PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
NXP Semiconductors 74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counterxxx
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NXP Semiconductors 74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
NXP Semiconductors 74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
5. Pinning information
5.1 Pinning
5.2 Pin description[1] LOW-to-HIGH, edge triggered.
Table 2. Pin description 15 data input 0 1 data input 1 10 data input 2 9 data input 3 3 flip-flop output 0 2 flip-flop output 1 6 flip-flop output 2 7 flip-flop output 3
CPD 4 count down clock input[1]
CPU 5 count up clock input[1]
GND 8 ground (0V) 11 asynchronous parallel load input (active LOW)
TCU 12 terminal count up (carry) output (active LOW)
TCD 13 terminal count down (borrow) output (active LOW) 14 asynchronous master reset input (active HIGH)
VCC 16 supply voltage
NXP Semiconductors 74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
6. Functional description[1] H = HIGH voltage level
L = LOW voltage level
X = don’t care
= LOW-to-HIGH clock transition.
[2] TCU= CPU at terminal count up (HHHH)
[3] TCD= CPD at terminal count down (LLLL).
Table 3. Function table[1]Reset (clear) H X X LX X X X LLLLH L X X H X X X X LLLLH H
Parallel load LLX LLL LLLLLLH L
LLX H LL LLLLLLH H
LLLX H H HHHHHHL H L HX HH HHHHHHHH
Count up L H H X X X X count up H[2] H
Count down L H H X X X X count down H H[3]
NXP Semiconductors 74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
NXP Semiconductors 74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
7. Limiting values[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP16 packages: above 70 C the value of Ptot derates linearly at 12 mW/K.
For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
8. Recommended operating conditions
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V or VI >VCC+ 0.5 V [1]- 20 mA
IOK output clamping current VO < 0.5 V or VO > VCC + 0.5V [1]- 20 mA output current VO = 0.5 V to VCC + 0.5 V - 25 mA
ICC supply current - 50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation DIP16 package [2] -750 mW
SO16 package [2] -500 mW
SSOP16 package [2] -500 mW
TSSOP16 package [2] -500 mW
Table 5. Recommended operating conditions
74HC193VCC supply voltage 2.0 5.0 6.0 V input voltage 0- VCC V output voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and
fall rate
VCC = 2.0 V - - 625 ns/V
VCC = 4.5 V - 1.67 139 ns/V
VCC = 6.0 V --83 ns/V
74HCT193VCC supply voltage 4.5 5.0 5.5 V input voltage 0- VCC V output voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and
fall rate
VCC = 4.5 V - 1.67 139 ns/V
NXP Semiconductors 74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
9. Static characteristicsTable 6. Static characteristics type 74HC193At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Tamb = 25 CVIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 V
VCC = 4.5 V - 2.1 1.35 V
VCC = 6.0 V - 2.8 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL -- -= 20 A; VCC = 2.0 V 1.9 2.0 - V= 20 A; VCC = 4.5 V 4.4 4.5 - V= 20 A; VCC = 6.0 V 5.9 6.0 - V
IO = 4.0 mA; VCC = 4.5 V 3.984.32- V
IO = 5.2 mA; VCC = 6.0 V 5.485.81- V
VOL LOW-level output voltage VI = VIH or VIL =20 A; VCC = 2.0 V - 0 0.1 V =20 A; VCC = 4.5 V - 0 0.1 V =20 A; VCC = 6.0 V - 0 0.1 V
IO = 4.0 mA; VCC = 4.5V - 0.15 0.26 V
IO = 5.2 mA; VCC = 6.0V - 0.16 0.26 V input leakage current VI =VCCor GND; VCC =6.0V - - 0.1 A
ICC supply current VI = VCC or GND; IO = 0A;
VCC =6.0V 8.0 A input capacitance - 3.5 - pF
Tamb = 40 C to +85 CVIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL= 20 A; VCC = 2.0 V 1.9 - - V= 20 A; VCC = 4.5 V 4.4 - - V= 20 A; VCC = 6.0 V 5.9 - - V
IO = 4.0 mA; VCC = 4.5V 3.84 - - V
IO = 5.2 mA; VCC = 6.0V 5.34 - - V
NXP Semiconductors 74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counterVOL LOW-level output voltage VI = VIH or VIL =20 A; VCC = 2.0 V - - 0.1 V =20 A; VCC = 4.5 V - - 0.1 V =20 A; VCC = 6.0 V - - 0.1 V
IO = 4.0 mA; VCC = 4.5V - - 0.33 V
IO = 5.2 mA; VCC = 6.0V - - 0.33 V input leakage current VI =VCCor GND; VCC =6.0V - - 1.0 A
ICC supply current VI = VCC or GND; IO = 0A;
VCC =6.0V 80 A
Tamb = 40 C to +125 C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL= 20 A; VCC = 2.0 V 1.9 - - V= 20 A; VCC = 4.5 V 4.4 - - V= 20 A; VCC = 6.0 V 5.9 - - V
IO = 4.0 mA; VCC = 4.5V 3.7 - - V
IO = 5.2 mA; VCC = 6.0V 5.2 - - V
VOL LOW-level output voltage VI = VIH or VIL =20 A; VCC = 2.0 V - - 0.1 V =20 A; VCC = 4.5 V - - 0.1 V =20 A; VCC = 6.0 V - - 0.1 V
IO = 4.0 mA; VCC = 4.5V - - 0.4 V
IO = 5.2 mA; VCC = 6.0V - - 0.4 V input leakage current VI =VCCor GND; VCC =6.0V - - 1.0 A
ICC supply current VI =VCCor GND; IO = 0 A;
VCC =6.0V - 160 A
Table 6. Static characteristics type 74HC193 …continuedAt recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Table 7. Static characteristics type 74HCT193At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Tamb = 25 CVIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V
VOH HIGH-level output voltage VI =VIHor VIL; VCC =4.5V= 20 A4.4 4.5 - V= 4.0 mA 3.984.32- V
NXP Semiconductors 74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counterVOL LOW-level output voltage VI =VIHor VIL; VCC =4.5V =20 A- 0 0.1 V= 4.0 mA - 0.15 0.26 V input leakage current VI =VCCor GND; VCC =5.5V - - 0.1 A
ICC supply current VI = VCC or GND; IO = 0A;
VCC =5.5V 8.0 A
ICC additional supply current per input pin; VI =VCC 2.1 V and
other inputs at VCCor GND; =0A; VCC= 4.5Vto 5.5V
pin Dn - 35 126 A
pins CPU, CPD - 140 504 A
pin PL - 65 234 A
pin MR - 105 378 A input capacitance - 3.5 - pF
Tamb = 40 C to +85 CVIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-level output voltage VI =VIHor VIL; VCC =4.5V= 20 A4.4 - - V= 4.0 mA 3.84 - - V
VOL LOW-level output voltage VI =VIHor VIL; VCC =4.5V =20 A- - 0.1 V= 4.0 mA - - 0.33 V input leakage current VI =VCCor GND; VCC =5.5V - - 1.0 A
ICC supply current VI = VCC or GND; IO = 0A;
VCC =5.5V 80 A
ICC additional supply current per input pin; VI =VCC 2.1 V and
other inputs at VCCor GND; =0A; VCC= 4.5Vto 5.5V
pin Dn - - 157.5 A
pins CPU, CPD - - 630 A
pin PL - - 292.5 A
pin MR - - 472.5 A
Tamb = 40 C to +125 CVIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-level output voltage VI =VIHor VIL; VCC =4.5V= 20 A4.4 - - V= 4.0 mA 3.7 - - V
VOL LOW-level output voltage VI =VIHor VIL; VCC =4.5V =20 A- - 0.1 V
IO = 4.0 mA - - 0.4 V
Table 7. Static characteristics type 74HCT193 …continuedAt recommended operating conditions; voltages are referenced to GND (ground = 0 V).
NXP Semiconductors 74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter input leakage current VI =VCCor GND; VCC =5.5V - - 1.0 A
ICC supply current VI = VCC or GND; IO = 0A;
VCC =5.5V - 160 A
ICC additional supply current per input pin; VI =VCC 2.1 V and
other inputs at VCCor GND; =0A; VCC= 4.5Vto 5.5V
pin Dn - - 171.5 A
pins CPU, CPD - - 686 A
pin PL - - 318.5 A
pin MR - - 514.5 A
Table 7. Static characteristics type 74HCT193 …continuedAt recommended operating conditions; voltages are referenced to GND (ground = 0 V).
NXP Semiconductors 74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
10. Dynamic characteristicsTable 8. Dynamic characteristics type 74HC193tpd propagation
delay
CPU, CPD to Qn;
see Figure9
[1] -
VCC= 2.0V - 63 215 - 270 - 325 ns
VCC= 4.5V - 23 43 - 54 - 65 ns
VCC= 6.0V - 18 37 - 46 - 55 ns
CPU to TCU; see
Figure10
VCC= 2.0V - 39 125 - 155 - 190 ns
VCC= 4.5V - 14 25 - 31 - 38 ns
VCC= 6.0V - 11 21 - 26 - 32 ns
CPD to TCD; see
Figure10
VCC= 2.0V - 39 125 - 155 - 190 ns
VCC= 4.5V - 14 25 - 31 - 38 ns
VCC= 6.0V - 11 21 - 26 - 32 ns to Qn; see
Figure11
VCC= 2.0V - 69 220 - 275 - 330 ns
VCC= 4.5V - 25 44 - 55 - 66 ns
VCC= 6.0V - 20 37 - 47 - 56 ns
MR to Qn; see
Figure12
VCC= 2.0V - 58 200 - 250 - 300 ns
VCC= 4.5V - 21 40 - 50 - 60 ns
VCC= 6.0V - 17 34 43 - 51 ns to Qn; see
Figure11
VCC= 2.0V - 69 210 - 265 - 315 ns
VCC= 4.5V - 25 42 - 53 - 63 ns
VCC= 6.0V - 20 36 - 45 - 54 ns to TCU,PLto
TCD; see Figure14
VCC= 2.0V - 80 290 - 365 - 435 ns
VCC= 4.5V - 29 58 - 73 - 87 ns
VCC= 6.0V - 23 49 - 62 - 74 ns
MR to TCU,MRto
TCD; see Figure14
VCC= 2.0V - 74 285 - 355 - 430 ns
VCC= 4.5V - 27 57 - 71 - 86 ns
VCC= 6.0V - 22 48 - 60 - 73 ns
NXP Semiconductors 74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down countertpd propagation
delay to TCU,Dnto
TCD; see Figure14
VCC= 2.0V - 80 290 - 365 - 435 ns
VCC= 4.5V - 29 58 - 73 - 87 ns
VCC= 6.0V - 23 49 - 62 - 74 ns
tTHL HIGH to LOW
output transition
time
see Figure12
VCC= 2.0V - 19 75 - 95 - 110 ns
VCC =4.5V - 7 15 - 19 - 22 ns
VCC =6.0V - 6 13 - 16 - 19 ns
tTLH LOW to HIGH
output transition
time
see Figure12
VCC= 2.0V - 19 75 - 95 - 110 ns
VCC =4.5V - 7 15 - 19 - 22 ns
VCC =6.0V - 6 13 - 16 - 19 ns pulse width CPU, CPD (HIGH
or LOW); see
Figure9
VCC= 2.0V 100 22 - 125 - 150 - ns
VCC =4.5V 20 8 - 25 - 30 - ns
VCC =6.0V 17 6 - 21 - 26 - ns
MR (HIGH); see
Figure12
VCC= 2.0V 100 25 - 125 - 150 - ns
VCC =4.5V 20 9 - 25 - 30 - ns
VCC =6.0V 17 7 - 21 - 26 - ns
PL (LOW); see
Figure11
VCC= 2.0V 100 19 - 125 - 150 - ns
VCC =4.5V 20 7 - 25 - 30 - ns
VCC =6.0V 17 6 - 21 - 26 - ns
trec recovery time PL to CPU, CPD;
see Figure11
VCC =2.0V 50 8 - 65 - 75 - ns
VCC =4.5V 10 3 - 13 - 15 - ns
VCC =6.0V 9 2 - 11 - 13 - ns
MR to CPU, CPD;
see Figure12
VCC =2.0V 50 0 - 65 - 75 - ns
VCC =4.5V 10 0 - 13 - 15 - ns
VCC =6.0V 9 0 - 11 - 13 - ns
Table 8. Dynamic characteristics type 74HC193 …continued
NXP Semiconductors 74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter[1] tpd is the same as tPHL and tPLH.
[2] CPD is used to determine the dynamic power dissipation (PD in W): =CPD VCC2fi N+ (CL VCC2 fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
tsu set-up time Dn to PL; see
Figure 13; note:
CPU = CPD=
HIGH
VCC= 2.0V 80 22 - 100 - 120 - ns
VCC =4.5V 16 8 - 20 - 24 - ns
VCC =6.0V 14 6 - 17 - 20 - ns hold time Dn to PL; see
Figure13
VCC =2.0V 0 14 - 0 - 0 - ns
VCC =4.5V 0 5- 0 - 0 - ns
VCC =6.0V 0 4- 0 0 - ns
CPU to CPD,
CPD to CPU; see
Figure15
VCC= 2.0V 80 22 - 100 - 120 - ns
VCC =4.5V 16 8 - 20 - 24 - ns
VCC =6.0V 8 6 - 17 - 20 - ns
fmax maximum
frequency
CPU, CPD; see
Figure9
VCC= 2.0V 4.0 13.5 - 3.2 - 2.6 - MHz
VCC =4.5V 20 41 - 16 - 13 - MHz
VCC =6.0V 24 49 - 19 - 15 - MHz
CPD power
dissipation
capacitance
VI = GND to VCC;
VCC =5V; =1 MHz
[2] -24- - - - - pF
Table 8. Dynamic characteristics type 74HC193 …continued
