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74HC174D-74HC174N
Hex D-type flip-flop with reset; positive-edge trigger
1. General descriptionThe 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual
data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs
load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold
time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and
appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW.
Inputs include clamp diodes. This enables the use of current limiting resistors to interface
inputs to voltages in excess of VCC.
2. Features and benefits Input levels: For 74HC174: CMOS level For 74HCT174: TTL level Six edge-triggered D-type flip-flops Asynchronous master reset Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V. Multiple package options Specified from 40 C to +85 C and 40 C to +125 C.
3. Ordering information
74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
Rev. 3 — 16 April 2013 Product data sheet
Table 1. Ordering information74HC174N 40 C to +125C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT174N
74HC174D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width
3.9 mm
SOT109-1
74HCT174D
74HC174DB 40 C to +125C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HCT174DB
74HC174PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT174PW
NXP Semiconductors 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
4. Functional diagramNXP Semiconductors 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 asynchronous master reset input (active LOW)
Q0 to Q5 2, 5, 7, 10, 12, 15 flip-flop output
D0 to D5 3, 4, 6, 11, 13, 14 data input
GND 8 ground (0 V) 9 clock input (LOW-to-HIGH edge-triggered)
VCC 16 positive supply voltage
NXP Semiconductors 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
6. Functional description[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
7. Limiting values[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP16 package: above 70 C the value of Ptot derates linearly with 12 mW/K.
[3] For SO16 package: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
Table 3. Function table[1]reset (clear) L X X L
load “1” H hH
load “0” H lL
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V)
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5V [1]- 20 mA
IOK output clamping current VO < 0.5 V or VO >VCC +0.5V [1]- 20 mA output current 0.5 V
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125C
DIP16 package [2]- 750 mW
SO16, SSOP16 and TSSOP16 [3]- 500 mW
NXP Semiconductors 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 - +125 40 - +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC174
VIH HIGH-level
input voltage
VCC = 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC = 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC =6.0V 0.1 - 1- 1 A
ICC supply current VI = VCC or GND; IO =0A;
VCC =6.0V - 8.0 - 80 - 160 A
NXP Semiconductors 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
10. Dynamic characteristics input
capacitance
-3.5 - - - - - pF
74HCT174
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = 20A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = 20 A; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA; VCC = 5.5V - 0.15 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC =5.5V 0.1 - 1- 1 A
ICC supply current VI = VCC or GND; IO =0A;
VCC =5.5V - 8.0 - 80 - 160 A
ICC additional
supply current
per input pin; =VCC 2.1V;
other inputs at VCC or GND;
VCC= 4.5Vto 5.5V
Dn input - 25 90 - 112.5 - 122.5 A
CP input - 130 468 - 585 - 637 A
MR input - 125 450 - 562.5 - 612.5 A input
capacitance
-3.5 - - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Table 7. Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure9
74HC174
tpd propagation
delay
CP to Qn; see Figure7 [1]
VCC = 2.0V - 55 165 - 205 - 250 ns
VCC = 4.5V - 20 33 - 41 - 50 ns
VCC = 5.0 V; CL =15pF - 17 - - - - - ns
VCC = 6.0V - 16 28 - 35 - 43 ns
NXP Semiconductors 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
tPHL HIGH to LOW
propagation
delay
MR to Qn; see Figure8
VCC = 2.0V - 44 150 - 190 - 225 ns
VCC = 4.5V - 16 30 - 38 - 45 ns
VCC = 5.0 V; CL =15pF - 13 - - - - - ns
VCC = 6.0V - 13 26 - 33 - 38 ns transition time Qn output; see Figure7 [2]
VCC = 2.0V - 19 75 - 95 - 110 ns
VCC = 4.5V - 7 15 - 19 - 22 ns
VCC = 6.0V - 6 13 - 16 - 19 ns pulse width CP input HIGHor LOW;
see Figure7
VCC = 2.0V 80 17 - 100 - 120 - ns
VCC = 4.5V 16 6 - 20 - 24 - ns
VCC = 6.0V 14 5 - 17 - 20 - ns
MR input LOW;
see Figure8
VCC = 2.0V 80 12 - 100 - 120 - ns
VCC = 4.5V 16 4 - 20 - 24 - ns
VCC = 6.0V 14 3 - 17 - 20 - ns
trec recovery time MR to CP; see Figure8
VCC = 2.0V 5 11 - 5 - 5 - ns
VCC = 4.5V 5 4- 5 - 5 - ns
VCC = 6.0V 5 3- 5 - 5 - ns
tsu set-up time Dn to CP; see Figure7
VCC = 2.0V 60 6 - 75 - 90 - ns
VCC = 4.5V 12 2 - 15 - 18 - ns
VCC = 6.0V 10 2 - 13 - 15 - ns hold time Dn to CP; see Figure7
VCC = 2.0V 3 6- 3 - 3 - ns
VCC = 4.5V 3 2- 3 - 3 - ns
VCC = 6.0V 3 2- 3 - 3 - ns
fmax maximum
frequency
CP input; see Figure7
VCC = 2.0V 6 30 - 5 - 4 - MHz
VCC = 4.5V 30 90 - 24 - 20 - MHz
VCC = 6.0V 35 107 - 28 - 24 - MHz
VCC = 5.0 V; CL =15pF - 99 - - - - - MHz
CPD power
dissipation
capacitance
per package; =GNDto VCC
[3] -17- - - - - pF
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure9
NXP Semiconductors 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC 2 fi + (CL VCC 2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC 2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
74HCT174
tpd propagation
delay
CP to Qn; see Figure7 [1]
VCC = 4.5V - 21 35 - 44 - 53 ns
VCC = 5.0 V; CL =15pF - 18 - - - - - ns
tPHL HIGH to LOW propagation delay
MR to Qn; see Figure8
VCC = 4.5V - 20 35 - 44 - 53 ns
VCC = 5.0 V; CL =15pF - 17 - - - - - ns transition time Qn output; see Figure7 [2]
VCC = 4.5V - 7 15 - 19 - 22 ns pulse width CP input; see Figure7
VCC = 4.5V 16 7 - 20 - 24 - ns
MR input LOW;
see Figure8
VCC = 4.5V 20 7 - 25 - 30 - ns
trec recovery time MR to CP; see Figure8
VCC = 4.5V 12 3 - 15 - 18 - ns
tsu set-up time Dn to CP; see Figure7
VCC = 4.5V 16 4 - 20 - 24 - ns hold time Dn to CP; see Figure7
VCC = 4.5V 5 3- 5 - 5 - ns
fmax maximum
frequency
CP input; see Figure7
VCC = 4.5 V 30 63 - 24 - 20 - MHz
VCC = 5.0 V; CL =15pF - 69 - - - - - MHz
CPD power
dissipation
capacitance
per package; =GNDto VCC 1.5 V
[3] -17- - - - - pF
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure9
NXP Semiconductors 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
11. Waveforms
