74HC173D ,Quad D-type flip-flop; positive-edge trigger; 3-stateGENERAL DESCRIPTIONThe 3-state output buffers are controlled by a 2-input NORThe 74HC/HCT173 are hi ..
74HC173D ,Quad D-type flip-flop; positive-edge trigger; 3-stateFEATURES synchronously with the LOW-to-HIGH clock (CP)transition. When one or both E inputs are HIG ..
74HC173D ,Quad D-type flip-flop; positive-edge trigger; 3-stateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC173N ,Quad D-type flip-flop; positive-edge trigger; 3-stateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC173N ,Quad D-type flip-flop; positive-edge trigger; 3-stateGENERAL DESCRIPTIONThe 3-state output buffers are controlled by a 2-input NORThe 74HC/HCT173 are hi ..
74HC174D ,Hex D-type flip-flop with reset; positive-edge triggerLogic diagram74HC_HCT174 All information provided in this document is subject to legal disclaimers. ..
74LVC16244ADGG ,16-bit buffer/line driver; 5V input/output tolerant 3-StatePIN CONFIGURATION• 5 volt tolerant inputs/outputs for interfacing with 5V logic1OE 1 48 2OE• Wide s ..
74LVC16244ADGGRG4 ,16-Bit Buffer/Driver With 3-State Outputs 48-TSSOP -40 to 125Maximum Ratings . 611 Power Supply Recommendations... 137.2 Handling Ratings. 612 Layout.... 137.3 ..
74LVC16244ADL ,16-bit buffer/line driver; 5 V input/output tolerant; 3-statePIN CONFIGURATION• 5 volt tolerant inputs/outputs for interfacing with 5V logic1OE 1 48 2OE• Wide s ..
74LVC16245ADGG ,16-bit bus transceiver with direction pin; 5 V tolerant; 3-statefeatures two output enable (nOE) inputs for easy cascading and two send/receive (nDIR) inputs for d ..
74LVC16245ADGGRG4 ,16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES062Q–DECEMBER 1995–REVISED JUNE 20146 Pin Configuration and FunctionsDGG, DGV, OR DL PACKAGE(T ..
74LVC16245ADGVRE4 ,16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTSMaximum Ratings . 611 Power Supply Recommendations... 137.2 Handling Ratings. 612 Layout.... 147.3 ..
74HC173D-74HC173N-74HCT173D-74HCT173N
Quad D-type flip-flop; positive-edge trigger; 3-state
Philips Semiconductors Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173
FEATURES Gated input enable for hold (do nothing) mode Gated output enable control Edge-triggered D-type register Asynchronous master reset Output capability: bus driver ICC category: MSI
GENERAL DESCRIPTIONThe 74HC/HCT173 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT173 are 4-bit parallel load registers with
clock enable control, 3-state buffered outputs (Q0 to Q3)
and master reset (MR).
When the two data enable inputs (E1 andE2) are LOW, the
data on the Dn inputs is loaded into the register
synchronously with the LOW-to-HIGH clock (CP)
transition. When one or both En inputs are HIGH one
set-up time prior to the LOW-to-HIGH clock transition, the
register will retain the previous data. Data inputs and clock
enable inputs are fully edge-triggered and must be stable
only one set-up time prior to the LOW-to-HIGH clock
transition.
The master reset input (MR) is an active HIGH
asynchronous input. When MR is HIGH, all four flip-flops
are reset (cleared) independently of any other input
condition.
The 3-state output buffers are controlled by a 2-input NOR
gate. When both output enable inputs (OE1 and OE2) are
LOW, the data in the register is presented to the Qn
outputs. When one or both OEn inputs are HIGH, the
outputs are forced to a high impedance OFF-state. The
3-state output buffers are completely independent of the
register operation; the OEn transition does not affect the
clock and reset operations.
QUICK REFERENCE DATAGND=0 V; Tamb =25 °C; tr =tf =6ns
Notes CPD is used to determine the dynamic power dissipation (PD in μW): =CPD× VCC2×fi +∑ (CL× VCC2× fo) where:= input frequency in MHz= output frequency in MHz (CL× VCC2×fo)= sum of outputs= output load capacitance in pF
VCC= supply voltage in V For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC −1.5V
ORDERING INFORMATION
Philips Semiconductors Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173
PIN DESCRIPTION
Philips Semiconductors Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173
FUNCTION TABLE
Notes H= HIGH voltage level= HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition= lower case letters indicate the state of the referenced input (or output)
one set-up time prior to the LOW-to-HIGH CP transition= don’t care= high impedance OFF-state= LOW-to-HIGH CP transition
Philips Semiconductors Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173
Philips Semiconductors Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173
DC CHARACTERISTICS FOR 74HCFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HCGND=0 V; tr =tf=6 ns; CL =50pF
