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74HC165D-74HC165PW
8-bit parallel-in/serial-out shift register
General descriptionThe 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with
JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC165; 74HCT165 are 8-bit parallel-load or serial-in shift registers with
complementary serial outputs (Q7 and Q7) available from the last stage. When the
parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the
register asynchronously.
When PLis HIGH, data enters the register seriallyat the DS input and shifts one placeto
the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the
succeeding stage.
The clock input is a gated-OR structure which allows one input to be used as an active
LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE
should only take place while CP HIGH for predictable operation. Either the CP or the CE
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
Features Asynchronous 8-bit parallel load Synchronous serial input Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V Specified from −40 °Cto+85 °C and from −40°Cto +125°C
Applications Parallel-to-serial data conversion
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Rev. 03 — 14 March 2008 Product data sheet
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register Ordering information Functional diagram
Table 1. Ordering information74HC165N −40 °C to +125°C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT165N
74HC165D −40 °C to +125°C SO16 plastic small outline package;16 leads; body width 3.9 mm SOT109-1
74HCT165D
74HC165DB −40 °C to +125°C SSOP16 plastic shrink small outline package; 16 leads; body width
5.3 mm
SOT338-1
74HCT165DB
74HC165PW −40 °C to +125°C TSSOP16 plastic thin shrink small outline package; 16 leads; body
width 4.4 mm
SOT403-1
74HCT165PW
74HC165BQ −40 °C to +125°C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 16 terminals; body
2.5× 3.5× 0.85 mm
SOT763-1
74HCT165BQ
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register Pinning information
6.1 Pinning
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
6.2 Pin description Functional description[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
↑ = LOW-to-HIGH clock transition.
Table 2. Pin description 1 asynchronous parallel load input (active LOW) 2 clock input (LOW-to-HIGH edge-triggered) 7 complementary output from the last stage
GND 8 ground (0 V) 9 serial output from the last stage 10 serial data input
D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs (also referred to as Dn) 15 clock enable input (active LOW)
VCC 16 positive supply voltage
Table 3. Function table[1]parallel load L XXXL L L to L L H XXXH H H to H H L
serial shift H L ↑ l X L q0 to q5 q6 q6 ↑ h X H q0 to q5 q6 q6 ↑ L l X L q0 to q5 q6 q6 ↑ L h X H q0 to q5 q6 q6
hold “do nothing” H H X X X q0 q1 to q6 q7 q7 X H X X q0 q1 to q6 q7 q7
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register Limiting values
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V)
VCC supply voltage −0.5 +7 V
IIK input clamping current VI < −0.5 V or VI >VCC+ 0.5V [1]- ±20 mA
IOK output clamping current VO < −0.5 V or VO >VCC+ 0.5V [1]- ±20 mA output current −0.5 V
ICC supply current - 50 mA
IGND ground current −50 - mA
Tstg storage temperature −65 +150 °C
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 12 mW/K above 70°C.
[3] Ptot derates linearly with 8 mW/K above 70°C.
[4] Ptot derates linearly with 5.5 mW/K above 60°C.
[5] Ptot derates linearly with 4.5 mW/K above 60°C. Recommended operating conditions
10. Static characteristics
Ptot total power dissipation Tamb = −40 °C to +125°C
DIP16 package [2]- 750 mW
SO16 package [3]- 500 mW
(T)SSOP16 package [4]- 500 mW
DHVQFN16 package [5]- 500 mW
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V)
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature −40 - +125 −40 - +125 °C
Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC165
VIH HIGH-level
input voltage
VCC = 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC = 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0V - 2.8 1.8 - 1.8 - 1.8 V
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
VOH HIGH-level
output voltage
VI = VIH or VIL
IO = −20 μA; VCC = 2.0V 1.9 2.0 - 1.9 - 1.9 - V
IO = −20 μA; VCC = 4.5V 4.4 4.5 - 4.4 - 4.4 - V
IO = −20 μA; VCC = 6.0V 5.9 6.0 - 5.9 - 5.9 - V
IO = −4.0 mA; VCC = 4.5V 3.98 4.32 - 3.84 - 3.7 - V
IO = −5.2 mA; VCC = 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage
VI = VIH or VIL
IO = 20 μA; VCC = 2.0V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 6.0V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC= 6.0V ±0.1 - ±1- ±1 μA
ICC supply current VI = VCC or GND; IO =0A;
VCC= 6.0V - 8.0 - 80 - 160 μA input
capacitance 3.5 - - - - - pF
74HCT165
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = −20μA 4.4 4.5 - 4.4 - 4.4 - V
IO = −4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = 20 μA; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA; VCC = 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC= 6.0V ±0.1 - ±1- ±1 μA
ICC supply current VI = VCC or GND; IO =0A;
VCC= 6.0V - 8.0 - 80 - 160 μA
ΔICC additional
supply current
per input pin; =VCC− 2.1V;
other inputsat VCCor GND;
VCC= 4.5Vto 5.5V
Dn and DS inputs - 35 126 - 157.5 - 171.5 μA CE, and PL inputs - 65 234 - 292.5 - 318.5 μA input
capacitance 3.5 - - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
11. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure12
74HC165
tpd propagation
delay
CP or CE to Q7, Q7;
see Figure7
[1]
VCC = 2.0V - 52 165 - 205 - 250 ns
VCC = 4.5V - 19 33 - 41 - 50 ns
VCC = 6.0V - 15 28 - 35 - 43 ns
VCC = 5.0 V; CL =15pF - 16 - - - - - ns
PL to Q7, Q7; see Figure8
VCC = 2.0V - 50 165 - 205 - 250 ns
VCC = 4.5V - 18 33 - 41 - 50 ns
VCC = 6.0V - 14 28 - 35 - 43 ns
VCC = 5.0 V; CL =15pF - 15 - - - - - ns
D7 to Q7, Q7; see Figure9
VCC = 2.0V - 36 120 - 150 - 180 ns
VCC = 4.5V - 13 24 - 30 - 36 ns
VCC = 6.0V - 10 20 - 26 - 31 ns
VCC = 5.0 V; CL =15pF - 11 - - - - - ns transition
time
Q7, Q7 output; see Figure7 [2]
VCC = 2.0V - 19 75 - 95 - 110 ns
VCC = 4.5V - 7 15 - 19 - 22 ns
VCC = 6.0V - 6 13 - 16 - 19 ns pulse width CP input HIGHor LOW;
see Figure7
VCC = 2.0V 80 17 - 100 - 120 - ns
VCC = 4.5V 16 6 - 20 - 24 - ns
VCC = 6.0V 14 5 - 17 - 20 - ns
PL input LOW; see Figure8
VCC = 2.0V 80 14 - 100 - 120 - ns
VCC = 4.5V 16 5 - 20 - 24 - ns
VCC = 6.0V 14 4 - 17 - 20 - ns
trec recovery time PL to CP, CE; see Figure8
VCC = 2.0V 100 22 - 125 - 150 - ns
VCC = 4.5V 20 8 - 25 - 30 - ns
VCC = 6.0V 17 6 - 21 - 26 - ns
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
tsu set-up time DS to CP, CE; see Figure10
VCC = 2.0V 80 11 - 100 - 120 - ns
VCC = 4.5V 16 4 - 20 - 24 - ns
VCC = 6.0V 14 3 - 17 - 20 - ns
CE to CP and CPto CE;
see Figure10
VCC = 2.0V 80 17 - 100 - 120 - ns
VCC = 4.5V 16 6 - 20 - 24 - ns
VCC = 6.0V 14 5 - 17 - 20 - ns
Dn to PL; see Figure11
VCC = 2.0V 80 22 - 100 - 120 - ns
VCC = 4.5V 16 8 - 20 - 24 - ns
VCC = 6.0V 14 6 - 17 - 20 - ns hold time DS to CP, CE and Dnto PL;
see Figure10
VCC = 2.0V 5 6 - 5 - 5 - ns
VCC = 4.5V 5 2 - 5 - 5 - ns
VCC = 6.0V 5 2 - 5 - 5 - ns
CE to CP and CPto CE;
see Figure10
VCC = 2.0V 5 −17 - 5 - 5 - ns
VCC = 4.5V 5 −6- 5 - 5 - ns
VCC = 6.0V 5 −5- 5 - 5 - ns
fmax maximum
frequency
CP input; see Figure7
VCC = 2.0V 6 17 - 5 - 4 - MHz
VCC = 4.5V 30 51 - 24 - 20 - MHz
VCC = 6.0V 35 61 - 28 - 24 - MHz
VCC = 5.0 V; CL=15pF - 56 - - - - - MHz
CPD power
dissipation
capacitance
per package;= GNDto VCC
[3] -35- - - - - pF
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure12
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
74HCT165
tpd propagation
delay
CE, CP to Q7, Q7;
see Figure7
[1]
VCC = 4.5V - 17 34 - 43 - 51 ns
VCC = 5.0 V; CL =15pF - 14 - - - - - ns
PL to Q7, Q7; see Figure8
VCC = 4.5V - 20 40 - 50 - 60 ns
VCC = 5.0 V; CL =15pF - 17 - - - - - ns
D7 to Q7, Q7; see Figure9
VCC = 4.5V - 14 28 - 35 - 42 ns
VCC = 5.0 V; CL =15pF - 11 - - - - - ns transition
time
Q7, Q7 output; see Figure7 [2]
VCC = 4.5V - 7 15 - 19 - 22 ns pulse width CP input; see Figure7
VCC = 4.5V 16 6 - 20 - 24 - ns
PL input; see Figure8
VCC = 4.5V 20 9 - 25 - 30 - ns
trec recovery time PL to CP, CE; see Figure8
VCC = 4.5V 20 8 - 25 - 30 - ns
tsu set-up time DS to CP, CE; see Figure10
VCC = 4.5V 20 2 - 25 - 30 - ns
CE to CP and CPto CE;
see Figure10
VCC = 4.5V 20 7 - 25 - 30 - ns
Dn to PL; see Figure11
VCC = 4.5V 20 10 - 25 - 30 - ns hold time DS to CP, CE and Dnto PL;
see Figure10
VCC = 4.5V 7 −1 - 9 - 11 - ns
CE to CP and CPto CE;
see Figure10
VCC = 4.5V 0 −7- 0 - 0 - ns
fmax maximum
frequency
CP input; see Figure7
VCC = 4.5 V 26 44 - 21 - 17 - MHz
VCC = 5.0 V; CL=15pF - 48 - - - - - MHz
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure12
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
Σ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC= supply voltage in V.
12. Waveforms
CPD power
dissipation
capacitance
per package;= GNDto VCC − 1.5 V
[3] -35- - - - - pF
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure12
