74HC164DB-74HC164N-74HC164PW-74HCT164D-74HCT164PW Fast Delivery |IC PHOENIX CO.,LIMITED

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74HC164DB-74HC164N-74HC164PW-74HCT164D-74HCT164PW
8-bit serial-in, parallel-out shift register
1. General description
The 74HC164; 74HCT164 is an 8-bit serial-in/parallel-out shift register. The device
features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7).
Data is entered serially through DSA or DSB and either input can be used as an active
HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH
transitions of the clock (CP) input. A LOW on the master reset input (MR) clears the
register and forces all outputs LOW, independently of other inputs. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
2. Features and benefits Input levels: For 74HC164: CMOS level For 74HCT164: TTL level Gated serial data inputs Asynchronous master reset Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V. Multiple package options Specified from 40 C to +85 C and 40 C to +125 C.
74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
Rev. 7 — 13 June 2013 Product data sheet
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
3. Ordering information
4. Functional diagram
Table 1. Ordering information
74HC164N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT164N
74HC164D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HCT164D
74HC164DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT337-1
74HCT164DB
74HC164PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74HCT164PW
74HC164BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.53 0.85 mm
SOT762-1
74HCT164BQ
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
5. Pinning information
5.1 Pinning
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition = LOW voltage level= LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition= lower case letters indicate the state of the referenced input one set-up time prior to the LOW-to-HIGH clock transition= LOW-to-HIGH clock transition
7. Limiting values
Table 2. Pin description
DSA 1 data input
DSB 2 data input
Q0 to Q7 3, 4, 5, 6, 10, 11, 12, 13 output
GND 7 ground (0 V) 8 clock input (LOW-to-HIGH, edge-triggered) 9 master reset input (active LOW)
VCC 14 positive supply voltage
Table 3. Function table[1]
Reset (clear) L XX XL LtoL
Shift H  ll L q0 to q6  lh L q0 to q6  hl Lq0 to q6  hh H q0 to q6
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V [1]- 20 mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V [1]- 20 mA output current 0.5 V < VO < VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60C.
8. Recommended operating conditions
9. Static characteristics
Ptot total power dissipation [2]
DIP14 package - 750 mW
SO14, (T)SSOP14 and
DHVQFN14 packages 500 mW
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V --83 - --ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC164
VIH HIGH-level
input voltage
VCC = 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC = 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0V - 2.8 1.8 - 1.8 - 1.8 V
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
VOH HIGH-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC =6.0V 0.1 - 1- 1 A
ICC supply current VI = VCC or GND; IO =0A;
VCC =6.0V - 8.0 - 80 - 160 A input
capacitance
-3.5 - - - - - pF
74HCT164
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = 20A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = 20 A; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA; VCC = 6.0V - 0.15 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC =6.0V 0.1 - 1- 1 A
ICC supply current VI = VCC or GND; IO =0A;
VCC =6.0V 8 - 80 - 160 A
ICC additional
supply current
per input pin; =VCC 2.1 V; IO =0A;
other inputs at VCC or GND;
VCC= 4.5Vto 5.5V 100 360 - 450 - 490 A input
capacitance
-3.5 - - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
10. Dynamic characteristicsTable 7. Dynamic characteristics
GND = 0 V; tr= tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified
74HC164
tpd propagation
delayto Qn; see Figure7 [1]
VCC = 2.0 V - 41 170 - 215 - 255 ns
VCC = 4.5 V - 15 34 - 43 - 51 ns
VCC = 5.0 V; CL =15pF - 12 - - - - - ns
VCC = 6.0 V - 12 29 - 37 - 43 ns
tPHL HIGH to LOW
propagation
delay to Qn; see Figure8
VCC = 2.0 V - 39 140 - 175 - 210 ns
VCC = 4.5 V - 14 28 - 35 - 42 ns
VCC = 5.0 V; CL =15pF - 11 - - - - - ns
VCC = 6.0 V - 11 24 - 30 - 36 ns transition time see Figure7 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns pulse width CP HIGHor LOW;
see Figure7
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
MR LOW; see Figure8
VCC = 2.0 V 60 17 - 75 - 90 - ns
VCC = 4.5 V 12 6 - 15 - 18 - ns
VCC = 6.0 V 10 5 - 13 - 15 - ns
trec recovery time MRto CP; see Figure8
VCC = 2.0 V 60 17 - 75 - 90 - ns
VCC = 4.5 V 12 6 - 15 - 18 - ns
VCC = 6.0 V 10 5 - 13 - 15 - ns
tsu set-up time DSA, and DSB to CP;
see Figure9
VCC = 2.0 V 60 8 - 75 - 90 - ns
VCC = 4.5 V 12 3 - 15 - 18 - ns
VCC = 6.0 V 10 2 - 13 - 15 - ns hold time DSA, and DSB to CP;
see Figure9
VCC = 2.0 V +4 6- 4 - 4 - ns
VCC = 4.5 V +4 2- 4 - 4 - ns
VCC = 6.0 V +4 2- 4 - 4 - ns
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
fmax maximum
frequency
for Cp, see Figure7
VCC = 2.0 V 6 23 - 5 - 4 - MHz
VCC = 4.5 V 30 71 - 24 - 20 - MHz
VCC = 5.0 V; CL =15pF - 78 - - - - - MHz
VCC = 6.0 V 35 85 - 28 - 24 - MHz
CPD power
dissipation
capacitance
per package; =GNDto VCC
[3] -40- - - - - pF
74HCT164
tpd propagation
delayto Qn; see Figure7 [1]
VCC = 4.5 V - 17 36 - 45 - 54 ns
VCC = 5.0 V; CL =15pF - 14 - - - - - ns
tPHL HIGH to LOW
propagation
delay to Qn; see Figure8
VCC = 4.5 V - 19 38 - 48 - 57 ns
VCC = 5.0 V; CL =15pF - 16 - - - - - ns transition time see Figure7 [2]
VCC = 4.5 V - 7 15 - 19 - 22 ns pulse width CP HIGHor LOW;
see Figure7
VCC = 4.5 V 18 7 - 23 - 27 - ns
MR LOW; see Figure8
VCC = 4.5 V 18 10 - 23 - 27 - ns
trec recovery time MRto CP; see Figure8
VCC = 4.5 V 16 7 - 20 - 24 - ns
tsu set-up time DSA, and DSB to CP;
see Figure9
VCC = 4.5 V 12 6 - 15 - 18 - ns hold time DSA, and DSB to CP;
see Figure9
VCC = 4.5 V +4 2- 4 - 4 - ns
fmax maximum
frequency
for Cp, see Figure7
VCC = 4.5 V 27 55 - 22 - 18 - MHz
VCC = 5.0 V; CL =15pF - 61 - - - - - MHz
Table 7. Dynamic characteristics …continued
GND = 0 V; tr= tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W): =CPD VCC2fi N+  (CL VCC2 fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;(CL VCC2fo)= sum of outputs.
CPD power
dissipation
capacitance
per package; =GNDto VCC 1.5V
[3] -40- - - - - pF
Table 7. Dynamic characteristics …continued
GND = 0 V; tr= tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified
Table 8. Measurement points
74HC164 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT164 1.3V 1.3V 0.1VCC 0.9VCC
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register

Partno	Mfg	Dc	Qty	Available	Descript
74HC164DB	NXP	N/a	172	avai	8-bit serial-in, parallel-out shift register
74HC164N	PH	N/a	17	avai	8-bit serial-in, parallel-out shift register
74HC164PW	NXP ?	N/a	166165	avai	74HC/HCT164; 8-bit serial-in/parallel-out shift register
74HCT164D	NXP	N/a	35545	avai	74HC/HCT164; 8-bit serial-in/parallel-out shift register
74HCT164PW	NXP	N/a	152	avai	74HC/HCT164; 8-bit serial-in/parallel-out shift register