74HC164 Fast Delivery |IC PHOENIX CO.,LIMITED

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74HC164
8 BIT SIPO SHIFT REGISTER
M54 HC164
M74HC164 BIT SIPO SHIFT REGISTER
B1R
(Plastic Package)
ORDER CODES:
M54HC164F1R M74HC164M1R
M74HC164B1R M74HC164C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)= Internal HIGH SPEED
tPD=15ns (TYP.) AT VCC =5V. LOWPOWER DISSIPATION
ICC =4 μA (MAX.) ATTA =25°C. OUTPUT DRIVE CAPABILITY LSTTL LOADS. BALANCEDPROPAGATION DELAYS
tPLH =tPHL. SYMMETRICAL OUTPUT IMPEDANCE
IOL= IOH=4 mA (MIN.). HIGH NOISE IMMUNITY
VNIH =VNIL =28% VCC (MIN.). WIDE OPERATING VOLTAGE RANGE
VCC (OPR)=2V TO6V. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS164
DESCRIPTION
The M54/74HC164isa high speed CMOS8 BIT
SIPO SHIFT REGISTER fabricatedin silicon gate2 MOS technology.It has thesame highspeed per-
formanceof LSTTL combined with true CMOS low
power consumption.
The HC164isan8bit shift register with serial data
entry andan output from eachof the eight stages.
Data isentered serially through oneof two inputs(A B), either ofthese inputs can beusedasan active
high enable for data entry through the other input. unused input mustbe high,or both inputs con-
nected together. Each low-to-high transitionon the
clock input shifts data one placeto the right and
entersintoQA, thelogic NAND ofthe two datainputs⋅ B), the data that existed before the rising clock
edge.A low level on the clear input overridesall
other inputs and clearsthe register asynchronously,
forcingallQ outputs low.
All inputs are equipped with protection circuits
INPUT AND OUTPUT EQUIVALENT CIRCUIT
TRUTH TABLE
INPUTS OUTPUS
CLEAR CLOCK SERIALIN QA QB ............ QHAB XXXL L ............ L X X NO CHANGE L X L QAn ............ QGn X L L QAn ............ QGn H H H QAn ............ QGn Don’tCare
QAn- QGn: Thelevel ofQA -QG,respectively. beforethe most-recent transitionofth clock.
LOGIC DIAGRAM
M54/M74HC164
PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION2 A,B Data Inputs4,5,6,
10,11, 12,to QH Outputs CLOCK Clock Input (LOWto
HIGH, Edge-triggered) CLEAR Master Reset Input GND Ground (0V) VCC Positive Supply Voltage
IEC LOGIC SYMBOL
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC Supply Voltage -0.5to+7 V DC Input Voltage -0.5to VCC+ 0.5 V DC Output Voltage -0.5to VCC+ 0.5 V
IIK DC Input Diode Current ±20 mA
IOK DC Output Diode Current ±20 mA DC Output Source Sink Current Per Output Pin ±25 mA
ICCor IGND DC VCCor Ground Current ±50 mA Power Dissipation 500(*) mW
Tstg Storage Temperature -65to +150 oC Lead Temperature (10 sec) 300 oC
Absolute MaximumRatings arethose values beyond whichdamage tothedevicemayoccur.Functional operation under theseconditionisnotimplied.
(*)500 mW:≅65oC derate to300mWby 10mW/oC:65o Cto85oC
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
VCC Supply Voltage 2to6 V Input Voltage 0to VCC V Output Voltage 0to VCC V
Top Operating Temperature: M54HC Series
M74HC Series
-55to +125
-40to +85CC
tr,tf Input Rise and Fall Time VCC=2V 0to 1000 ns
VCC=4.5V 0to 500
VCC=6V 0to 400
M54/M74HC164
SPECIFICATIONSSymbol Parameter
Test Conditions Value
UnitVCC
(V) =25oC
54HC and 74HC
-40to85oC
74HC
-55to 125oC
54HC
Min. Typ. Max. Min. Max. Min. Max.
VIH High Level Input
Voltage
2.0 1.5 1.5 1.54.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
VIL Low Level Input
Voltage
2.0 0.5 0.5 0.54.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
VOH High Level
Output Voltage
2.0 VI=
VIH
VIL
IO=-20μA
1.9 2.0 1.9 1.94.5 4.4 4.5 4.4 4.4
6.0 5.9 6.0 5.9 5.9
4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10
6.0 IO=-5.2 mA 5.68 5.8 5.63 5.60
VOL Low Level Output
Voltage
2.0 VI=
VIH
VIL
IO=20μA
0.0 0.1 0.1 0.14.5 0.0 0.1 0.1 0.1
6.0 0.0 0.1 0.1 0.1
4.5 IO= 4.0 mA 0.17 0.26 0.33 0.40
6.0 IO= 5.2 mA 0.18 0.26 0.33 0.40 Input Leakage
Current 6.0 VI =VCCor GND ±0.1 ±1 ±1 μA
ICC Quiescent Supply
Current
6.0 VI =VCCor GND 4 40 80 μA
M54/M74HC164
ELECTRICAL CHARACTERISTICS (CL =50 pF, Inputtr =tf =6 ns)Symbol Parameter
Test Conditions Value
UnitVCC
(V) =25oC
54HC and 74HC
-40to85oC
74HC
-55to 125oC
54HC
Min. Typ. Max. Min. Max. Min. Max.
tTLH
tTHL
Output Transition
Time
2.0 30 75 95 1104.5 8 151922
6.0 7 131619
tPLH
tPHL
Propagation
Delay Time
(CLOCK-Q)
2.0 57 160 200 2404.5 19 32 40 48
6.0 16 27 34 41
tPHL Propagation
Delay Time
(CLEAR-Q)
2.0 60 175 220 2654.5 20 35 44 53
6.0 17 30 37 45
fMAX Maximum Clock
Frequency
2.0 6.2 18 5.0 4.2
MHz4.5 31 53 25 21
6.0 37 62 30 25
tW(H)
tW(L)
Minimum Pulse
Width
(CLOCK)
2.0 24 75 95 1104.5 6 151922
6.0 5 131619
tW(L) Minimum Pulse
Width
(CLEAR)
2.0 40 75 95 1104.5 10 15 19 22
6.0 9 131619 Minimum Set-up
Time
(A,B- CK)
2.0 16 50 65 754.5 4 101315
6.0 3 9 11 13 Minimum Hold
Time
(A,B- CK)
2.0 5 5 54.5 5 5 5
6.0 5 5 5
tREM Minimum
Removal Time
2.0 5 5 54.5 5 5 5
6.0 5 5 5
CIN Input Capacitance 5 10 10 10 pF
CPD(*) Power Dissipation
Capacitance pF
(*) CPD isdefinedasthe valueofthe IC’sinternal equivalent capacitance which iscalculated fromthe operatingcurrent consumption without load.
(Referto Test Circuit).Average operting currentcanbe obtained bythefollowingequation. ICC(opr)=CPD •VCC •fIN+ICC
M54/M74HC164
TIMING CHART
M54/M74HC164

Partno	Mfg	Dc	Qty	Available	Descript
74HC164	NXP	N/a	500	avai	8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS