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74HC163N
Presettable synchronous 4-bit binary counter; synchronous reset
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset 74HC/HCT163
FEATURES Synchronous counting and loading Two count enable inputs for n-bit cascading Positive-edge triggered clock Synchronous reset Output capability: standard ICC category: MSI
GENERAL DESCRIPTIONThe 74HC/HCT163 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT163 are synchronous presettable binary
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q0 to Q3) of the counters may be preset to a
HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the
data at the data inputs (D0 to D3) to be loaded into the
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements for PE are met).
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
For the “163” the clear function is synchronous.
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q0 to Q3) to LOW level after the
next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for
MR are met). This action occurs regardless of the levels at
PE, CET and CEP inputs.
This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND
gate.
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q0. This
pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
fmax 1P max() (CPtoTC)tSU (CEPto CP)+ -------------------------------------------------------------------------------------------------=
QUICK REFERENCE DATAGND=0 V; Tamb =25 °C; tr =tf =6ns
Notes CPD is used to determine the
dynamic power dissipation
(PD in μW): =CPD× VCC2×fi+ (CL× VCC2×fo)
where:= input frequency in MHz= output frequency in MHz (CL× VCC2×fo)= sum of
outputs= output load capacitance in
VCC= supply voltage in V For HC the condition is= GND to VCC
For HCT the condition is= GND to VCC− 1.5V
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset 74HC/HCT163
ORDERING INFORMATIONSee “74HC/HCT/HCU/HCMOS Logic Package Information”.
PIN DESCRIPTION
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset 74HC/HCT163
FUNCTION TABLE
Notes The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH).= HIGH voltage level= HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition= LOW voltage level= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition= lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition= don’t care= LOW-to-HIGH CP transition
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset 74HC/HCT163
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset 74HC/HCT163
